Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 177
Documentation Changes
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
D1 /7 SAR r/m16,1 A Valid Valid Signed divide* r/m16 by 2,
once.
D3 /7 SAR r/m16, CL B Valid Valid Signed divide* r/m16 by 2,
CL times.
C1 /7 ib SAR r/m16, imm8 C Valid Valid Signed divide*
r/m16 by 2,
imm8 times.
D1 /7 SAR r/m32, 1 A Valid Valid Signed divide* r/m32 by 2,
once.
REX.W + D1 /7 SAR r/m64, 1 A Valid N.E. Signed divide* r/m64 by 2,
once.
D3 /7 SAR r/m32, CL B Valid Valid Signed divide*
r/m32 by 2,
CL times.
REX.W + D3 /7 SAR r/m64, CL B Valid N.E. Signed divide*
r/m64 by 2,
CL times.
C1 /7 ib SAR r/m32, imm8 C Valid Valid Signed divide*
r/m32 by 2,
imm8 times.
REX.W + C1 /7
ib
SAR r/m64, imm8 C Valid N.E. Signed divide*
r/m64 by 2,
imm8 times
D0 /4 SHL r/m8, 1 A Valid Valid Multiply r/m8 by 2, once.
REX + D0 /4 SHL r/m8**, 1 A Valid N.E. Multiply r/m8 by 2, once.
D2 /4 SHL r/m8, CL B Valid Valid Multiply r/m8 by 2, CL times.
REX + D2 /4 SHL r/m8**, CL B Valid N.E. Multiply r/m8 by 2, CL times.
C0 /4 ib SHL r/m8, imm8 CValid Valid Multiply r/m8 by 2, imm8
times.
REX + C0 /4 ib SHL r/m8**, imm8 CValid N.E. Multiply r/m8 by 2, imm8
times.
D1 /4 SHL r/m16,1 A Valid Valid Multiply r/m16 by 2, once.
D3 /4 SHL r/m16, CL B Valid Valid Multiply r/m16 by 2, CL
times.
C1 /4 ib SHL r/m16, imm8 CValid Valid Multiply r/m16 by 2, imm8
times.
D1 /4 SHL r/m32,1 A Valid Valid Multiply r/m32 by 2, once.
REX.W + D1 /4 SHL r/m64,1 A Valid N.E. Multiply r/m64 by 2, once.
D3 /4 SHL r/m32, CL B Valid Valid Multiply r/m32 by 2, CL
times.
REX.W + D3 /4 SHL r/m64, CL B Valid N.E. Multiply r/m64 by 2, CL
times.
C1 /4 ib SHL r/m32, imm8 CValid Valid Multiply r/m32 by 2, imm8
times.
REX.W + C1 /4
ib
SHL r/m64, imm8
CValid N.E. Multiply r/m64 by 2, imm8
times.
D0 /5 SHR r/m8,1 A Valid Valid Unsigned divide r/m8 by 2,
once.