Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 176
Documentation Changes
Instruction Operand Encoding
...
SAL/SAR/SHL/SHR—Shift
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Opcode*** Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
D0 /4 SAL r/m8, 1 A Valid Valid Multiply r/m8 by 2, once.
REX + D0 /4 SAL r/m8**, 1 A Valid N.E. Multiply r/m8 by 2, once.
D2 /4 SAL r/m8, CL B Valid Valid Multiply r/m8 by 2, CL times.
REX + D2 /4 SAL r/m8**, CL B Valid N.E. Multiply r/m8 by 2, CL times.
C0 /4 ib SAL r/m8, imm8 CValid Valid Multiply r/m8 by 2, imm8
times.
REX + C0 /4 ib SAL r/m8**, imm8 CValid N.E. Multiply r/m8 by 2, imm8
times.
D1 /4 SAL r/m16, 1 A Valid Valid Multiply r/m16 by 2, once.
D3 /4 SAL r/m16, CL B Valid Valid Multiply r/m16 by 2, CL
times.
C1 /4 ib SAL r/m16, imm8 CValid Valid Multiply r/m16 by 2, imm8
times.
D1 /4 SAL r/m32, 1 A Valid Valid Multiply r/m32 by 2, once.
REX.W + D1 /4 SAL r/m64, 1 A Valid N.E. Multiply r/m64 by 2, once.
D3 /4 SAL r/m32, CL B Valid Valid Multiply r/m32 by 2, CL
times.
REX.W + D3 /4 SAL r/m64, CL B Valid N.E. Multiply r/m64 by 2, CL
times.
C1 /4 ib SAL r/m32, imm8 CValid Valid Multiply r/m32 by 2, imm8
times.
REX.W + C1 /4
ib
SAL r/m64, imm8 CValid N.E. Multiply r/m64 by 2, imm8
times.
D0 /7 SAR r/m8, 1 A Valid Valid Signed divide* r/m8 by 2,
once.
REX + D0 /7 SAR r/m8**, 1 A Valid N.E. Signed divide* r/m8 by 2,
once.
D2 /7 SAR r/m8, CL B Valid Valid Signed divide* r/m8 by 2, CL
times.
REX + D2 /7 SAR r/m8**, CL B Valid N.E. Signed divide* r/m8 by 2, CL
times.
C0 /7 ib SAR r/m8, imm8 C Valid Valid Signed divide* r/m8 by 2,
imm8 time.
REX + C0 /7 ib SAR r/m8**, imm8 C Valid N.E. Signed divide* r/m8 by 2,
imm8 times.