Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 169
Documentation Changes
RDTSC—Read Time-Stamp Counter
Instruction Operand Encoding
Description
Loads the current value of the processor’s time-stamp counter (a 64-bit MSR) into the
EDX:EAX registers. The EDX register is loaded with the high-order 32 bits of the MSR and
the EAX register is loaded with the low-order 32 bits. (On processors that support the
Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.)
The processor monotonically increments the time-stamp counter MSR every clock cycle
and resets it to 0 whenever the processor is reset. See “Time Stamp Counter” in Chapter
16 of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B,
for specific details of the time stamp counter behavior.
When in protected or virtual 8086 mode, the time stamp disable (TSD) flag in register
CR4 restricts the use of the RDTSC instruction as follows. When the TSD flag is clear, the
RDTSC instruction can be executed at any privilege level; when the flag is set, the
instruction can only be executed at privilege level 0. (When in real-address mode, the
RDTSC instruction is always enabled.)
The time-stamp counter can also be read with the RDMSR instruction, when executing at
privilege level 0.
The RDTSC instruction is not a serializing instruction. It does not necessarily wait until all
previous instructions have been executed before reading the counter. Similarly, subse-
quent instructions may begin execution before the read operation is performed. If soft-
ware requires RDTSC to be executed only after all previous instructions have completed
locally, it can either use RDTSCP (if the processor supports that instruction) or execute
the sequence LFENCE;RDTSC.
This instruction was introduced by the Pentium processor.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 22 of the
Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, for more
information about the behavior of this instruction in VMX non-root operation.
...
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 31 RDTSC A Valid Valid Read time-stamp counter
into EDX:EAX.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA