Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 167
Documentation Changes
The performance-monitoring counters are event counters that can be programmed to
count events such as the number of instructions decoded, number of interrupts received,
or number of cache loads. Appendix A, “Performance Monitoring Events,” in the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, lists the events
that can be counted for various processors in the Intel 64 and IA-32 architecture fami-
lies.
The RDPMC instruction is not a serializing instruction; that is, it does not imply that all
the events caused by the preceding instructions have been completed or that events
caused by subsequent instructions have not begun. If an exact event count is desired,
software must insert a serializing instruction (such as the CPUID instruction) before and/
or after the RDPMC instruction.
In the Pentium 4 and Intel Xeon processors, performing back-to-back fast reads are not
guaranteed to be monotonic. To guarantee monotonicity on back-to-back reads, a serial-
izing instruction must be placed between the two RDPMC instructions.
The RDPMC instruction can execute in 16-bit addressing mode or virtual-8086 mode;
however, the full contents of the ECX register are used to select the counter, and the
event count is stored in the full EAX and EDX registers. The RDPMC instruction was intro-
duced into the IA-32 Architecture in the Pentium Pro processor and the Pentium
processor with MMX technology. The earlier Pentium processors have performance-
monitoring counters, but they must be read with the RDMSR instruction.
Operation
(* Intel Core i7 processor family and Intel Xeon processor 3400, 5500 series*)
Most significant counter bit (MSCB) = 47
IF ((CR4.PCE
= 1) or (CPL = 0) or (CR0.PE = 0))
THEN IF (ECX[30]
= 1 and ECX[29:0] in valid fixed-counter range)
EAX ← IA32_FIXED_CTR(ECX)[30:0];
EDX ← IA32_FIXED_CTR(ECX)[MSCB:32];
ELSE IF (ECX[30]
= 0 and ECX[29:0] in valid general-purpose counter range)
EAX ← PMC(ECX[30:0])[31:0];
EDX ← PMC(ECX[30:0])[MSCB:32];
ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
#GP(0);
FI;
(* Intel Core 2 Duo processor family and Intel Xeon processor 3000, 5100, 5300, 7400 series*)
Most significant counter bit (MSCB) = 39
IF ((CR4.PCE
= 1) or (CPL = 0) or (CR0.PE = 0))
THEN IF (ECX[30]
= 1 and ECX[29:0] in valid fixed-counter range)
EAX ← IA32_FIXED_CTR(ECX)[30:0];
EDX ← IA32_FIXED_CTR(ECX)[MSCB:32];
ELSE IF (ECX[30]
= 0 and ECX[29:0] in valid general-purpose counter range)
EAX ← PMC(ECX[30:0])[31:0];
EDX ← PMC(ECX[30:0])[MSCB:32];
ELSE IF (ECX[30]
= 0 and ECX[29:0] in valid special-purpose counter range)
EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)