Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 165
Documentation Changes
Instruction Operand Encoding
Description
The EAX register is loaded with the low-order 32 bits. The EDX register is loaded with the
supported high-order bits of the counter. The number of high-order bits loaded into EDX
is implementation specific on processors that do no support architectural performance
monitoring. The width of fixed-function and general-purpose performance counters on
processors supporting architectural performance monitoring are reported by CPUID 0AH
leaf. See below for the treatment of the EDX register for “fast” reads.
The ECX register selects one of two type of performance counters, specifies the index
relative to the base of each counter type, and selects “fast” read mode if supported. The
two counter types are :
• General-purpose or special-purpose performance counters: The number of general-
purpose counters is model specific if the processor does not support architectural
performance monitoring, see Chapter 30 of Intel
®
64 and IA-32 Architectures
Software Developer’s Manual, Volume 3B. Special-purpose counters are available
only in selected processor members, see Section 30.13, 30.14 of Intel
®
64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B. This counter type is
selected if ECX[30] is clear.
• Fixed-function performance counter. The number fixed-function performance
counters is enumerated by CPUID 0AH leaf. See Chapter 30 of Intel
®
64 and IA-32
Architectures Software Developer’s Manual, Volume 3B. This counter type is selected
if ECX[30] is set.
ECX[29:0] specifies the index. The width of general-purpose performance counters are
40-bits for processors that do not support architectural performance monitoring
counters.The width of special-purpose performance counters are implementation
specific. The width of fixed-function performance counters and general-purpose perfor-
mance counters on processor supporting architectural performance monitoring are
reported by CPUID 0AH leaf.
Table 4-2 lists valid indices of the general-purpose and special-purpose performance
counters according to the derived displayed_family/displayed_model values of CPUID
encoding for each processor family.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Table 4-2 Valid General and Special Purpose Performance Counter Index Range for
RDPMC
Processor Family Displayed_Family_Dis
played_Model/ Other
Signatures
Valid PMC
Index Range
General-
purpose
Counters
P6 06H_01H, 06H_03H,
06H_05H, 06H_06H,
06H_07H, 06H_08H,
06H_0AH, 06H_0BH
0, 1 0, 1
Pentium
®
4, Intel
®
Xeon
processors
0FH_00H, 0FH_01H,
0FH_02H
≥ 0 and ≤ 17 ≥ 0 and ≤ 17
Pentium 4, Intel Xeon processors (0FH_03H, 0FH_04H,
0FH_06H) and (L3 is
absent)
≥ 0 and ≤ 17 ≥ 0 and ≤ 17