Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 161
Documentation Changes
Opcode** Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
C1 /2 ib RCL r/m32, imm8 CValid Valid Rotate 33 bits (CF, r/m32)
left imm8 times.
REX.W + C1 /2
ib
RCL r/m64, imm8 C Valid N.E. Rotate 65 bits (CF, r/m64)
left imm8 times. Uses a 6 bit
count.
D0 /3 RCR r/m8, 1 A Valid Valid Rotate 9 bits (CF, r/m8) right
once.
REX + D0 /3 RCR r/m8*, 1 A Valid N.E. Rotate 9 bits (CF, r/m8) right
once.
D2 /3 RCR r/m8, CL B Valid Valid Rotate 9 bits (CF, r/m8) right
CL times.
REX + D2 /3 RCR r/m8*, CL B Valid N.E. Rotate 9 bits (CF, r/m8) right
CL times.
C0 /3 ib RCR r/m8, imm8 CValid Valid Rotate 9 bits (CF, r/m8) right
imm8 times.
REX + C0 /3 ib RCR r/m8*, imm8 C Valid N.E. Rotate 9 bits (CF, r/m8) right
imm8 times.
D1 /3 RCR r/m16, 1 A Valid Valid Rotate 17 bits (CF, r/m16)
right once.
D3 /3 RCR r/m16, CL B Valid Valid Rotate 17 bits (CF, r/m16)
right CL times.
C1 /3 ib RCR r/m16, imm8 CValid Valid Rotate 17 bits (CF, r/m16)
right imm8 times.
D1 /3 RCR r/m32, 1 A Valid Valid Rotate 33 bits (CF, r/m32)
right once. Uses a 6 bit
count.
REX.W + D1 /3 RCR
r/m64, 1 A Valid N.E. Rotate 65 bits (CF, r/m64)
right once. Uses a 6 bit
count.
D3 /3 RCR r/m32, CL B Valid Valid Rotate 33 bits (CF, r/m32)
right CL times.
REX.W + D3 /3 RCR r/m64, CL B Valid N.E. Rotate 65 bits (CF, r/m64)
right CL times. Uses a 6 bit
count.
C1 /3 ib RCR r/m32, imm8 CValid Valid Rotate 33 bits (CF, r/m32)
right imm8 times.
REX.W + C1 /3
ib
RCR r/m64, imm8 C Valid N.E. Rotate 65 bits (CF, r/m64)
right imm8 times. Uses a 6
bit count.
D0 /0 ROL r/m8, 1 A Valid Valid Rotate 8 bits r/m8 left once.
REX + D0 /0 ROL r/m8*, 1 A Valid N.E. Rotate 8 bits r/m8 left once
D2 /0 ROL r/m8, CL B Valid Valid Rotate 8 bits r/m8 left CL
times.
REX + D2 /0 ROL r/m8*, CL B Valid N.E. Rotate 8 bits r/m8 left CL
times.