Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 160
Documentation Changes
PXOR—Logical Exclusive OR
Instruction Operand Encoding
...
RCL/RCR/ROL/ROR-—Rotate
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F EF /r PXOR mm,
mm/m64
A Valid Valid Bitwise XOR of mm/m64
and mm.
66 0F EF /r PXOR xmm1,
xmm2/m128
A Valid Valid Bitwise XOR of
xmm2/m128 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode** Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
D0 /2 RCL r/m8, 1 A Valid Valid Rotate 9 bits (CF, r/m8) left
once.
REX + D0 /2 RCL r/m8*, 1 A Valid N.E. Rotate 9 bits (CF, r/m8) left
once.
D2 /2 RCL r/m8, CL B Valid Valid Rotate 9 bits (CF, r/m8) left
CL times.
REX + D2 /2 RCL r/m8*, CL B Valid N.E. Rotate 9 bits (CF, r/m8) left
CL times.
C0 /2 ib RCL r/m8, imm8 CValid Valid Rotate 9 bits (CF, r/m8) left
imm8 times.
REX + C0 /2 ib RCL r/m8*, imm8 C Valid N.E. Rotate 9 bits (CF, r/m8) left
imm8 times.
D1 /2 RCL r/m16, 1 A Valid Valid Rotate 17 bits (CF, r/m16)
left once.
D3 /2 RCL r/m16, CL B Valid Valid Rotate 17 bits (CF, r/m16)
left CL times.
C1 /2 ib RCL r/m16, imm8 CValid Valid Rotate 17 bits (CF, r/m16
)
left imm8 times.
D1 /2 RCL r/m32, 1 A Valid Valid Rotate 33 bits (CF, r/m32)
left once.
REX.W + D1 /2 RCL r/m64, 1 A Valid N.E. Rotate 65 bits (CF, r/m64)
left once. Uses a 6 bit count.
D3 /2 RCL r/m32, CL B Valid Valid Rotate 33 bits (CF, r/m32)
left CL times.
REX.W + D3 /2 RCL r/m64, CL B Valid N.E. Rotate 65 bits (CF, r/m64)
left CL times. Uses a 6 bit
count.