Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 159
Documentation Changes
Instruction Operand Encoding
...
PUSHA/PUSHAD—Push All General-Purpose Registers
Instruction Operand Encoding
...
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack
Instruction Operand Encoding
...
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA
Breg (r) NA NA NA
C imm8/16/32 NA NA NA
DNA NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
60 PUSHA A Invalid Valid Push AX, CX, DX, BX, original
SP, BP, SI, and DI.
60 PUSHAD A Invalid Valid Push EAX, ECX, EDX, EBX,
original ESP, EBP, ESI, and
EDI.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
9C PUSHF A Valid Valid Push lower 16 bits of
EFLAGS.
9C PUSHFD A N.E. Valid Push EFLAGS.
9C PUSHFQ A Valid N.E. Push RFLAGS.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA