Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 152
Documentation Changes
Instruction Operand Encoding
...
PSRLDQ—Shift Double Quadword Right Logical
Instruction Operand Encoding
...
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:r/m (r, w) imm8 NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 73 /3 ib PSRLDQ xmm1,
imm8
AValid Valid Shift xmm1 right by imm8
while shifting in 0s.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r, w) imm8 NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F D1 /r PSRLW mm,
mm/m64
A Valid Valid Shift words in mm right by
amount specified in
mm/m64 while shifting in
0s.
66 0F D1 /r PSRLW xmm1,
xmm2/m128
A Valid Valid Shift words in xmm1 right
by amount specified in
xmm2/m128 while shifting
in 0s.
0F 71 /2 ib PSRLW mm, imm8 B Valid Valid Shift words in mm right by
imm8 while shifting in 0s.
66 0F 71 /2 ib PSRLW xmm1,
imm8
B Valid Valid Shift words in xmm1 right
by imm8 while shifting in 0s.
0F D2 /r PSRLD mm,
mm/m64
A Valid Valid Shift doublewords in mm
right by amount specified in
mm/m64 while shifting in
0s.
66 0F D2 /r PSRLD xmm1,
xmm2/m128
A Valid Valid Shift doublewords in xmm1
right by amount specified in
xmm2 /m128 while shifting
in 0s.
0F 72 /2 ib PSRLD mm, imm8 B Valid Valid Shift doublewords in
mm
right by imm8 while shifting
in 0s.