Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 15
Documentation Changes
ADDPS—Add Packed Single-Precision Floating-Point Values
Instruction Operand Encoding
...
ADDSD—Add Scalar Double-Precision Floating-Point Values
Instruction Operand Encoding
...
ADDSS—Add Scalar Single-Precision Floating-Point Values
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
0F 58 /r ADDPS xmm1,
xmm2/m128
A Valid Valid Add packed single-precision
floating-point values from
xmm2/m128 to xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
F2 0F 58 /r ADDSD xmm1,
xmm2/m64
A Valid Valid Add the low double-
precision floating-point
value from xmm2/m64 to
xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
F3 0F 58 /r ADDSS xmm1,
xmm2/m32
A Valid Valid Add the low single-precision
floating-point value from
xmm2/m32 to xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA