Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 14
Documentation Changes
Instruction Operand Encoding
...
ADDPD—Add Packed Double-Precision Floating-Point Values
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
REX.W + 83 /0
ib
ADD r/m64, imm8 BValid N.E. Add sign-extended imm8 to
r/m64.
00 /r ADD r/m8, r8 AValid Valid Add r8 to r/m8.
REX + 00 /r ADD r/m8
*
, r8
*
AValid N.E. Add r8 to r/m8.
01 /r ADD r/m16, r16 AValid Valid Add r16 to r/m16.
01 /r ADD r/m32, r32 AValid Valid Add r32 to r/m32.
REX.W + 01 /r ADD r/m64, r64 AValid N.E. Add r64 to r/m64.
02 /r ADD r8, r/m8 AValid Valid Add r/m8 to r8.
REX + 02 /r ADD r8
*
, r/m8
*
AValid N.E. Add r/m8 to r8.
03 /r ADD r16, r/m16 AValid Valid Add r/m16 to r16.
03 /r ADD r32, r/m32 AValid Valid Add r/m32 to r32.
REX.W + 03 /r ADD r64, r/m64 AValid N.E. Add r/m64 to r64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:r/m (r, w) imm8 NA NA
C AL/AX/EAX/RAX imm8 NA NA
Opcode Instruction Op/
En
64-bit
Mode
Compat/
Leg Mode
Description
66 0F 58 /r ADDPD xmm1,
xmm2/m128
A Valid Valid Add packed double-precision
floating-point values from
xmm2/m128 to xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA