Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 127
Documentation Changes
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15, R8-15). PEXTRQ requires REX.W. If the
destination operand is a general-purpose register, the default operand size of PEXTRB/
PEXTRW is 64 bits.
...
PEXTRW—Extract Word
Instruction Operand Encoding
...
PHADDW/PHADDD — Packed Horizontal Add
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F C5 /r ib PEXTRW reg, mm,
imm8
A Valid Valid Extract the word specified
by imm8 from mm and move
it to reg, bits 15-0. The
upper bits of r32 or r64 is
zeroed.
66 0F C5 /r ib PEXTRW reg,
xmm, imm8
A Valid Valid Extract the word specified
by imm8 from xmm and
move it to reg, bits 15-0.
The upper bits of r32 or r64
is zeroed.
66 0F 3A 15
/r ib
PEXTRW reg/m16,
xmm, imm8
B Valid Valid Extract the word specified
by imm8 from xmm and
copy it to lowest 16 bits of
reg or m16. Zero-extend
the result in the destination,
r32 or r64.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:reg (r) imm8 NA
B ModRM:r/m (w) ModRM:reg (r) imm8 NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 38 01 /r PHADDW mm1,
mm2/m64
A Valid Valid Add 16-bit signed integers
horizontally, pack to MM1.
66 0F 38 01 /r PHADDW xmm1,
xmm2/m128
A Valid Valid Add 16-bit signed integers
horizontally, pack to XMM1.
0F 38 02 /r PHADDD mm1,
mm2/m64
A Valid Valid Add 32-bit signed integers
horizontally, pack to MM1.
66 0F 38 02 /r PHADDD xmm1,
xmm2/m128
A Valid Valid Add 32-bit signed integers
horizontally, pack to XMM1.