Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 121
Documentation Changes
PANDN—Logical AND NOT
Instruction Operand Encoding
...
PAUSE—Spin Loop Hint
Instruction Operand Encoding
...
PAVGB/PAVGW—Average Packed Integers
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F DF /r PANDN mm,
mm/m64
A Valid Valid Bitwise AND NOT of
mm/m64 and mm.
66 0F DF /r PANDN xmm1,
xmm2/m128
A Valid Valid Bitwise AND NOT of
xmm2/m128 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F3 90 PAUSE A Valid Valid Gives hint to processor that
improves performance of
spin-wait loops.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F E0 /r PAVGB mm1,
mm2/m64
A Valid Valid Average packed unsigned
byte integers from
mm2/m64 and mm1 with
rounding.
66 0F E0, /r PAVGB xmm1,
xmm2/m128
A Valid Valid Average packed unsigned
byte integers from
xmm2/m128 and xmm1
with rounding.
0F E3 /r PAVGW mm1,
mm2/m64
A Valid Valid Average packed unsigned
word integers from
mm2/m64 and mm1 with
rounding.
66 0F E3 /r PAVGW xmm1,
xmm2/m128
A Valid Valid Average packed unsigned
word integers from
xmm2/m128 and xmm1
with rounding.