Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 120
Documentation Changes
Instruction Operand Encoding
...
PALIGNR — Packed Align Right
Instruction Operand Encoding
...
PAND—Logical AND
Instruction Operand Encoding
...
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 3A 0F PALIGNR mm1,
mm2/m64, imm8
A Valid Valid Concatenate destination and
source operands, extract
byte-aligned result shifted
to the right by constant
value in imm8 into mm1.
66 0F 3A 0F PALIGNR xmm1,
xmm2/m128,
imm8
A Valid Valid Concatenate destination and
source operands, extract
byte-aligned result shifted
to the right by constant
value in imm8 into xmm1
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) imm8 NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F DB /r PAND mm,
mm/m64
A Valid Valid Bitwise AND mm/m64 and
mm.
66 0F DB /r PAND xmm1,
xmm2/m128
A Valid Valid Bitwise AND of
xmm2/m128 and xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA