Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 114
Documentation Changes
Instruction Operand Encoding
...
IA-32 Architecture Compatibility
After executing an OUT instruction, the Pentium
®
processor ensures that the EWBE# pin
has been sampled active before it begins to execute the next instruction. (Note that the
instruction can be prefetched if EWBE# is not active, but it will not be executed until the
EWBE# pin is sampled active.) Only the Pentium processor family has the EWBE# pin.
...
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port
Op/En Operand 1 Operand 2 Operand 3 Operand 4
Aimm8 NA NA NA
BNA NA NA NA
Opcode* Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
6E OUTS DX, m8 A Valid Valid Output byte from memory
location specified in DS:(E)SI
or RSI to I/O port specified in
DX**.
6F OUTS DX, m16 A Valid Valid Output word from memory
location specified in DS:(E)SI
or RSI to I/O port specified in
DX**.
6F OUTS DX, m32 A Valid Valid Output doubleword from
memory location specified in
DS:(E)SI or RSI to I/O port
specified in DX**.
6E OUTSB A Valid Valid Output byte from memory
location specified in DS:(E)SI
or RSI to I/O port specified in
DX**.
6F OUTSW A Valid Valid Output word from memory
location specified in DS:(E)SI
or RSI to I/O port specified in
DX**.
6F OUTSD A Valid Valid Output doubleword from
memory location specified in
DS:(E)SI or RSI to I/O port
specified in DX**.
NOTES:
* See IA-32 Architecture Compatibility section below.
**In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) address sizes are supported. In non-64-bit
mode, only 32-bit (ESI) and 16-bit (SI) address sizes are supported.