Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 112
Documentation Changes
OR—Logical Inclusive OR
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0C ib OR AL, imm8 AValid Valid AL OR imm8.
0D iw OR AX, imm16 AValid Valid AX OR imm16.
0D id OR EAX, imm32 AValid Valid EAX OR imm32.
REX.W + 0D id OR RAX, imm32 AValid N.E. RAX OR imm32 (sign-
extended).
80 /1 ib OR r/m8, imm8 BValid Valid r/m8 OR imm8.
REX + 80 /1 ib OR r/m8*, imm8 BValid N.E. r/m8 OR imm8.
81 /1 iw OR r/m16, imm16 BValid Valid r/m16 OR imm16.
81 /1 id OR r/m32, imm32 BValid Valid r/m32 OR imm32.
REX.W + 81 /1
id
OR r/m64, imm32 BValid N.E. r/m64 OR imm32 (sign-
extended).
83 /1 ib OR r/m16, imm8 BValid Valid r/m16 OR imm8 (sign-
extended).
83 /1 ib OR r/m32, imm8 BValid Valid r/m32 OR imm8 (sign-
extended).
REX.W + 83 /1
ib
OR r/m64, imm8 BValid N.E. r/m64 OR imm8 (sign-
extended).
08 /r OR r/m8, r8 CValid Valid r/m8 OR r8.
REX + 08 /r OR r/m8*, r8* CValid N.E. r/m8 OR r8.
09 /r OR r/m16, r16 CValid Valid r/m16 OR r16.
09 /r OR r/m32, r32 CValid Valid r/m32 OR r32.
REX.W + 09 /r OR r/m64, r64 CValid N.E. r/m64 OR r64.
0A /r OR r8, r/m8 DValid Valid r8 OR r/m8.
REX + 0A /r OR r8*, r/m8* DValid N.E. r8 OR r/m8.
0B /r OR r16, r/m16 DValid Valid r16 OR r/m16.
0B /r OR r32, r/m32 DValid Valid r32 OR r/m32.
REX.W + 0B /r OR r64, r/m64 DValid N.E. r64 OR r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A AL/AX/EAX/RAX imm8/16/32 NA NA
B ModRM:r/m (r, w) imm8/16/32 NA NA
C ModRM:r/m (r, w) ModRM:reg (r) NA NA
D ModRM:reg (r, w) ModRM:r/m (r) NA NA