Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 110
Documentation Changes
MWAIT—Monitor Wait
Instruction Operand Encoding
...
2. Updates to Chapter 4, Volume 2B
Change bars show changes to Chapter 4 of the Intel
®
64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 2B: Instruction Set Reference, N-Z.
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NEG—Two's Complement Negation
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F 01 C9 MWAIT A Valid Valid A hint that allow the
processor to stop
instruction execution and
enter an implementation-
dependent optimized state
until occurrence of a class of
events.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
ANA NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F6 /3 NEG r/m8 A Valid Valid Two's complement negate
r/m8.
REX + F6 /3 NEG r/m8* A Valid N.E. Two's complement negate
r/m8.
F7 /3 NEG r/m16 A Valid Valid Two's complement negate
r/m16.
F7 /3 NEG r/m32 A Valid Valid Two's complement negate
r/m32.
REX.W + F7 /3 NEG r/m64 A Valid N.E. Two's complement negate
r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.