Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 108
Documentation Changes
MUL—Unsigned Multiply
Instruction Operand Encoding
...
MULPD—Multiply Packed Double-Precision Floating-Point Values
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F6 /4 MUL r/m8 A Valid Valid Unsigned multiply (AX AL
r/m8).
REX + F6 /4 MUL r/m8
*
A Valid N.E. Unsigned multiply (AX AL
r/m8).
F7 /4 MUL r/m16 A Valid Valid Unsigned multiply (DX:AX
AX r/m16).
F7 /4 MUL r/m32 A Valid Valid Unsigned multiply (EDX:EAX
EAX r/m32).
REX.W + F7 /4 MUL r/m64 A Valid N.E. Unsigned multiply (RDX:RAX
RAX r/m64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:r/m (r) NA NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 59 /r MULPD xmm1,
xmm2/m128
A Valid Valid Multiply packed double-
precision floating-point
values in xmm2/m128 by
xmm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA