Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 107
Documentation Changes
MOVZX—Move with Zero-Extend
Instruction Operand Encoding
...
MPSADBW — Compute Multiple Packed Sums of Absolute Difference
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
0F B6 /r MOVZX r16, r/m8 A Valid Valid Move byte to word with
zero-extension.
0F B6 /r MOVZX r32, r/m8 A Valid Valid Move byte to doubleword,
zero-extension.
REX.W + 0F B6
/r
MOVZX r64, r/m8* A Valid N.E. Move byte to quadword,
zero-extension.
0F B7 /r MOVZX r32,
r/m16
A Valid Valid Move word to doubleword,
zero-extension.
REX.W + 0F B7
/r
MOVZX r64,
r/m16
A Valid N.E. Move word to quadword,
zero-extension.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if the REX prefix
is used: AH, BH, CH, DH.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 3A 42 /r
ib
MPSADBW xmm1,
xmm2/m128,
imm8
A Valid Valid Sums absolute 8-bit integer
difference of adjacent
groups of 4 byte integers in
xmm1 and xmm2/m128
and writes the results in
xmm1. Starting offsets
within xmm1 and
xmm2/m128 are
determined by imm8.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) imm8 NA