Specifications

Intel
®
64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 103
Documentation Changes
MOVSD—Move Scalar Double-Precision Floating-Point Value
Instruction Operand Encoding
...
MOVSHDUP—Move Packed Single-FP High and Duplicate
Instruction Operand Encoding
...
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 10 /r MOVSD xmm1,
xmm2/m64
A Valid Valid Move scalar double-
precision floating-point
value from xmm2/m64 to
xmm1 register.
F2 0F 11 /r MOVSD
xmm2/m64,
xmm1
B Valid Valid Move scalar double-
precision floating-point
value from xmm1 register
to xmm2/m64.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA
B ModRM:r/m (w) ModRM:reg (r) NA NA
Opcode Instruction Op/
En
64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F 16 /r MOVSHDUP
xmm1,
xmm2/m128
A Valid Valid Move two single-precision
floating-point values from
the higher 32-bit operand of
each qword in xmm2/m128
to xmm1 and duplicate each
32-bit operand to the lower
32-bits of each qword.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA