Specifications

Errata
46 Intel
®
Core
™
2 Duo Processor
Specification Update
AW76. A Page Fault May Not be Generated When the PS bit is set to “1” in a
PML4E or PDPTE
Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7)
is reserved in PML4Es and PDPTEs. If the translation of the linear address of a
memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault
should occur. Due to this erratum, PS of such an entry is ignored and no
page fault will occur due to its being set.
Implication: Software may not operate properly if it relies on the processor to deliver page
faults when reserved bits are set in paging-structure entries.
Workaround: Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit
0) set to “1”.
Status: For the steppings affected, see the Summary Tables of Changes.
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