Specifications

Errata
Intel
®
Core
™
2 Duo Processor
Specification Update 45
Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE context
only, may not follow program order and may execute before older stores.
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW74. Memory Ordering Violation With Stores/Loads Crossing a Cacheline
Boundary
Problem: When two logical processors are accessing the same data that is crossing a
cacheline boundary without serialization, with a specific set of processor
internal conditions, it is possible to have an ordering violation between
memory store and load operations.
Implication: Due to this erratum, proper load/store ordering may not be followed when
multiple logical processors are accessing the same data that crosses a
cacheline boundary without serialization.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AW75. Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
Problem: The act of one processor, or system bus master, writing data into a currently
executing code segment of a second processor with the intent of having the
second processor execute that data as code is called cross-modifying code
(XMC). XMC that does not force the second processor to execute a
synchronizing instruction, prior to execution of the new code, is called
unsynchronized XMC.
Software using unsynchronized XMC to modify the instruction byte stream of
a processor can see unexpected or unpredictable execution behavior from the
processor that is executing the modified code.
Implication: In this case, the phrase "unexpected or unpredictable execution behavior"
encompasses the generation of most of the exceptions listed in the Intel
Architecture Software Developer's Manual Volume 3: System Programming
Guide, including a General Protection Fault (GPF) or other unexpected
behaviors. In the event that unpredictable execution causes a GPF the
application executing the unsynchronized XMC operation would be terminated
by the operating system.
Workaround: In order to avoid this erratum, programmers should use the XMC
synchronization algorithm as detailed in the Intel Architecture Software
Developer's Manual Volume 3: System Programming Guide, Section:
Handling Self- and Cross-Modifying Code.
Status: For the steppings affected, see the Summary Tables of Changes.