Specifications

Errata
Intel
®
Core
™
2 Duo Processor
Specification Update 43
AW68. INIT Incorrectly Resets IA32_LSTAR MSR
Problem: In response to an INIT reset initiated either via the INIT# pin or an IPI (Inter
Processor Interrupt), the processor should leave MSR values unchanged. Due
to this erratum IA32_LSTAR MSR (C0000082H), which is used by the iA32e
SYSCALL instruction, is being cleared by an INIT reset.
Implication: If software programs a value in IA32_LSTAR to be used by the SYSCALL
instruction and the processor subsequently receives an INIT reset, the
SYSCALL instructions will not behave as intended. Intel has not observed this
erratum in any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AW69. Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
Problem: During the transition from real mode to protected mode, if an SMI (System
Management Interrupt) occurs between the MOV to CR0 that sets
PE (Protection Enable, bit 0) and the first far JMP, the subsequent RSM
(Resume from System Management Mode) may cause the lower two bits of
CS segment register to be corrupted.
Implication: The corruption of the bottom two bits of the CS segment register will have no
impact unless software explicitly examines the CS segment register
between enabling protected mode and the first far JMP. Intel® 64 and IA-32
Architectures Software Developer’s Manual Volume 3A: System Programming
Guide, Part 1, in the section titled "Switching to Protected
Mode" recommends the far JMP immediately follows the write to CR0 to
enable protected mode. Intel has not observed this erratum with any
commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW70. LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
Problem: An exception/interrupt event should be transparent to the LBR (Last Branch
Record), BTS (Branch Trace Store) and BTM (Branch Trace Message)
mechanisms. However, during a specific boundary condition where the
exception/interrupt occurs right after the execution of an instruction at the
lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR
return registers will save a wrong return address with bits 63 to 48
incorrectly sign extended to all 1’s. Subsequent BTS and BTM operations
which report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an
exception/interrupt.