Specifications

Errata

42 Intel

Core

™

2 Duo Processor

Specification Update

AW65. Global Instruction TLB Entries May Not be Invalidated on a VM Exit or

VM Entry

Problem: If a VMM is using global page entries (CR4.PGE is enabled and any present

page-directories or page-table entries are marked global), then on a VM

entry, the instruction TLB (Translation Lookaside Buffer) entries caching

global page translations of the VMM may not be invalidated. In addition, if a

guest is using global page entries, then on a VM exit, the instruction TLB

entries caching global page translations of the guest may not be invalidated.

Implication: Stale global instruction linear to physical page translations may be used by a

VMM after a VM exit or a guest after a VM entry.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

AW66. When Intel® Deep Power-Down State is Being Used,

IA32_FIXED_CTR2 May Return Incorrect Cycle Counts

Problem: When the processor is operating at an N/2 core to front side bus ratio, after

exiting an Intel Deep Power-Down State, the internal increment value for

IA32_FIXED_CTR2 (Fixed Function Performance Counter 2, 30BH) will not

take into account the half ratio setting.

Implication: Due to this erratum, IA32_FIXED_CTR2 MSR will not return reliable counts

after returning from an Intel Deep Power-Down State.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

AW67. Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May

Corrupt the CPUID Feature Flags

Problem: Writing PECI_CTL MSR (Platform Environment Control Interface Control

the VMM Feature Flag Mask MSR (CPUID_FEATURE_MASK1, 478H).

Implication: Due to this erratum, PECI (Platform Environment Control Interface) will not

be enabled as expected by the software. In addition, due to this erratum,

processor features reported in ECX following execution of leaf 1 of CPUID

(EAX=1) may be masked. Software utilizing CPUID leaf 1 to verify processor

capabilities may not work as intended.

Workaround: It is possible for the BIOS to contain a workaround for this erratum. Do not

initialize PECI before processor update is loaded. Also, load processor update

as soon as possible after RESET as documented in the RS – Wolfdale

Processor Family Bios Writers Guide, Section 14.8.3 Bootstrap Processor

Initialization Requirements.

Status: For the steppings affected, see the Summary Tables of Changes.