Specifications

Errata
36 Intel
®
Core
™
2 Duo Processor
Specification Update
Problem: RSM instruction execution, under certain conditions triggered by a complex
sequence of internal processor micro-architectural events, may lead to
processor hang, or unexpected instruction execution results.
Implication: In the above sequence, the processor may live lock or hang, or RSM
instruction may restart the interrupted processor context through a
nondeterministic EIP offset in the code segment, resulting in unexpected
instruction execution, unexpected exceptions or system hang. Intel has not
observed this erratum with any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AW50. Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
Problem: According to the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A, “Exception and Interrupt Reference”, if another
exception occurs while attempting to call the double-fault handler, the
processor enters shutdown mode. However due to this erratum, only
Contributory Exceptions and Page Faults will cause a triple fault shutdown,
whereas a benign exception may not.
Implication: If a benign exception occurs while attempting to call the double-fault
handler, the processor may hang or may handle the benign exception. Intel
has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW51. Short Nested Loops That Span Multiple 16-Byte Boundaries May
Cause a Machine Check Exception or a System Hang
Problem: Under a rare set of timing conditions and address alignment of instructions in
a short nested loop sequence, software that contains multiple conditional
jump instructions and spans multiple 16-byte boundaries, may cause a
machine check exception or a system hang.
Implication: Due to this erratum, a machine check exception or a system hang may occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AW52. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug
breakpoints until after execution of the following instruction. This is intended
to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP,