Specifications

Errata
Intel
®
Core
™
2 Duo Processor
Specification Update 35
Problem: If instructions from at least three different ways in the same instruction cache
set exist in the pipeline combined with some rare internal state, self-
modifying code (SMC) or cross-modifying code may not be detected and/or
handled.
Implication: An instruction that should be overwritten by another instruction while in the
processor pipeline may not be detected/modified, and could retire without
detection. Alternatively the instruction may cause a Machine Check
Exception. Intel has not observed this erratum with any commercially
available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AW47. Data TLB Eviction Condition in the Middle of a Cacheline Split Load
Operation May Cause the Processor to Hang
Problem: If the TLB translation gets evicted while completing a cacheline split load
operation, under rare scenarios the processor may hang.
Implication: The cacheline split load operation may not be able to complete normally, and
the machine may hang and generate Machine Check Exception. Intel has not
observed this erratum with any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AW48. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present
(P) Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Problem: Updating a page table entry by changing R/W, U/S or P bits, even when
transitioning these bits from 0 to 1, without keeping the affected linear
address range coherent with all TLB (Translation Lookaside Buffers) and
paging-structures caches in the processor, in conjunction with a complex
sequence of internal processor micro-architectural events and store
operations, may lead to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor
behavior. Intel has not observed this erratum with any commercially
available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW49. RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results