Specifications

Errata
30 Intel
®
Core
™
2 Duo Processor
Specification Update
Problem: CPUID leaf 0Ah reports the architectural performance monitoring version that
is available in EAX[7:0]. Due to this erratum CPUID reports the supported
version as 2 instead of 1.
Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in
comparison to which features are actually supported.
Workaround: Software should use the recommended enumeration mechanism described in
the Architectural Performance Monitoring section of the Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 3: System Programming
Guide.
Status: For the steppings affected, see the Summary Tables of Changes.
AW35. B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly
Set
Problem: Some of the B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6
may be incorrectly set for non-enabled breakpoints when the following
sequence happens:
1. MOV or POP instruction to SS (Stack Segment) selector;
2. Next instruction is FP (Floating Point) that gets FP assist
3. Another instruction after the FP instruction completes successfully
4. A breakpoint occurs due to either a data breakpoint on the preceding
instruction or a code breakpoint on the next instruction.
Due to this erratum a non-enabled breakpoint triggered on step 1 or step 2
may be reported in B0-B3 after the breakpoint occurs in step 4.
Implication: Due to this erratum, B0-B3 bits in DR6 may be incorrectly set for non-
enabled breakpoints.
Workaround: Software should not execute a floating point instruction directly after a MOV
SS or POP SS instruction.
Status: For the steppings affected, see the Summary Tables of Changes.
AW36. An xTPR Update Transaction Cycle, if Enabled, May be Issued to the
FSB after the Processor has Issued a Stop-Grant Special Cycle
Problem: According to the FSB (Front Side Bus) protocol specification, no FSB cycles
should be issued by the processor once a Stop-Grant special cycle has been
issued to the bus. If xTPR update transactions are enabled by clearing the
IA32_MISC_ENABLES[bit 23] at the time of Stop-Clock assertion, an xTPR
update transaction cycle may be issued to the FSB after the processor has
issued a Stop Grant Acknowledge transaction.
Implication: When this erratum occurs in systems using C-states C2 (Stop-Grant State)
and higher the result could be a system hang.