Specifications

Summary Tables of Changes
14 Intel
®
Core
™
2 Duo Processor
Specification Update
NO
C0 M0 E0 R0 Plan
ERRATA
AW67 X X No Fix
Enabling PECI via the PECI_CTL MSR incorrectly
writes CPUID_FEATURE_MASK1 MSR
AW68 X X No Fix INIT Incorrectly Resets IA32_LSTAR MSR
AW69 X X X X No Fix
Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
AW70 X X X X No Fix
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AW71 X X No Fix
The XRSTOR Instruction May Fail to Cause a General-
Protection Exception
AW72 X X No Fix
The XSAVE Instruction May Erroneously Set Reserved Bits
in the XSTATE_BV Field
AW73 X X No Fix Store Ordering Violation When Using XSAVE
AW74 X X X X No Fix
Memory Ordering Violation With Stores/Loads Crossing a
Cacheline Boundary
AW75 X X Plan Fix
Unsynchronized Cross-Modifying Code Operations Can
Cause Unexpected Instruction Execution Results
AW76 X X X X No Fix
A Page Fault May Not be Generated When the PS bit is set
to “1” in a PML4E or PDPTE
Number SPECIFICATION CHANGES
- There are no Specification Changes in this Specification Update revision.
Number SPECIFICATION CLARIFICATIONS
AW1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Number DOCUMENTATION CHANGES
- There are no Documentation Changes in this Specification Update revision.
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