Specifications

Summary Tables of Changes
12 Intel
®
Core
™
2 Duo Processor
Specification Update
NO
C0 M0 E0 R0 Plan
ERRATA
AW25 X X X X No Fix
Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
AW26 X X X X No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be
Serviced Before Higher Priority Interrupts
AW27 X X X X No Fix
VERW/VERR/LSL/LAR Instructions May Unexpectedly
Update the Last Exception Record (LER) MSR
AW28 X X X X No Fix INIT Does Not Clear Global Entries in the TLB
AW29 X X X X No Fix
Split Locked Stores May not Trigger the Monitoring
Hardware
AW30 X X X X No Fix
Programming the Digital Thermal Sensor (DTS) Threshold
May Cause Unexpected Thermal Interrupts
AW31 X X X X No Fix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue
AW32 X X X X No Fix
General Protection (#GP) Fault May Not Be Signaled on
Data Segment Limit Violation above 4-G Limit
AW33 X X X X No Fix
An Asynchronous MCE During a Far Transfer May Corrupt
ESP
AW34 X X X X Plan Fix
CPUID Reports Architectural Performance
Monitoring Version 2 is Supported, When Only Version 1
Capabilities are Available
AW35 X X X X No Fix
B0-B3 Bits in DR6 May Not be Properly Cleared After Code
Breakpoint
AW36 X X X X No Fix
An xTPR Update Transaction Cycle, if Enabled, May be
Issued to the FSB after the Processor has Issued a Stop-
Grant Special Cycle
AW37 X X Fixed
Performance Monitoring Event IA32_FIXED_CTR2 May Not
Function Properly when Max Ratio is a Non-Integer Core-to-
Bus Ratio
AW38 X X X X No Fix
Instruction Fetch May Cause a Livelock During Snoops of
the L1 Data Cache
AW39 X X X X No Fix
Use of Memory Aliasing with Inconsistent Memory Type may
Cause a System Hang or a Machine Check Exception
AW40 X X X X No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May
Lead to Memory-Ordering Violations
AW41 X Fixed
VM Exit with Exit Reason “TPR Below Threshold” Can Cause
the Blocking by MOV/POP SS and Blocking by STI Bits to be
Cleared in the Guest Interruptibility-State Field
AW42 X X X X No Fix
Using Memory Type Aliasing with cacheable and WC
Memory Types May Lead to Memory Ordering Violations
AW43 X X No Fix
VM Exit Caused by a SIPI Results in Zero to be Saved to the
Guest RIP Field in the VMCS
AW44 X X Fixed NMIs May Not Be Blocked by a VM-Entry Failure