Intel® Core™2 Duo Processor E8000Δ and E7000Δ Series Specification Update — on 45 nm Process in the 775-land LGA Package June 2009 Notice: The Intel® CoreTM2 Duo processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Intel® Core™2 Duo Processor Specification Update 3
Contents Contents .............................................................................................................................4 Revision History ...................................................................................................................5 Preface ...............................................................................................................................6 Summary Tables of Changes ......................................................................
Revision History Revision Number Description Initial release of Intel® Core™2 Duo Desktop Processor E8000 Series Specification Update 001 Date Jan 7th 2008 Feb 1st 2008 002 Added Erratum AW51 003 Added Errata AW52 to AW54 Feb 13th 2008 004 Changed document title to include E7000 series Included E7200 and E8300 processor information April 20th 2008 005 Included M0 stepping information Added new errata AW55-AW57 May 14th 2008 Added Spec Clarification AW1 006 Updated Erratum AW
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for qualification and early design validation.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Item Numbering Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor specification updates: A= Dual-Core Intel® Xeon® processor 7000 sequence C= Intel® Celeron® processor D= Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor technology AH = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 sequence Quad-Core Intel® Xeon® processor 5300 series Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor Q6000 sequence Dual-Core Intel® Xeon® processor 7100 series AI = AJ = AK = AL = AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® dual-core p
Summary Tables of Changes NO C0 M0 E0 R0 Plan ERRATA AW4 X X X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order AW5 X X X X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault AW6 X X X X No Fix Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF AW7 X X X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI AW8 X X X X No Fix Performan
Summary Tables of Changes 12 NO C0 M0 E0 R0 Plan AW25 X X X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt AW26 X X X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts AW27 X X X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR AW28 X X X X No Fix INIT Does Not Clear Global Entries in the TLB AW29 X X X
Summary Tables of Changes NO C0 M0 Plan ERRATA AW45 X X Fixed Partial Streaming Load Instruction Sequence May Cause the Processor to Hang AW46 X X Fixed Self/Cross Modifying Code May Not be Detected or May Cause a Machine Check Exception AW47 X X Fixed Data TLB Eviction Condition in the Middle of a Cacheline Split Load Operation May Cause the Processor to Hang AW48 X X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexp
Summary Tables of Changes NO C0 M0 ERRATA E0 R0 Plan AW67 X X No Fix Enabling PECI via the PECI_CTL MSR incorrectly writes CPUID_FEATURE_MASK1 MSR AW68 X X No Fix INIT Incorrectly Resets IA32_LSTAR MSR AW69 X X X X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode AW70 X X X X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode AW71 X X No Fix The XRSTOR Instruction May Fa
Identification Information Identification Information Figure 1.
Component Identification Information Component Identification Information The Intel® Core™2 duo processor can be identified by the following values: Reserved Extended Family1 31:28 Extended Reserved Model2 27:20 19:16 00000000b 0001b 15:14 Processor Type3 Family Code4 Model Number5 Stepping ID6 13:12 11:8 7:4 3:0 00b 0110b 0111b XXXXb When EAX is initialized to a value of 1, the CPUID instruction returns the Extended Family, Extended Model, Type, Family, Model and Stepping value in the E
Component Identification Information Table 1. Intel® Core™2 Duo Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number Speed Core/Bus Package Notes SLAPC M0 3 MB 10676h E7200 2.53 GHz / 1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13 SLB9X M0 3 MB 10676h E7300 2.66 GHz / 1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13 SLAQR C0 6 MB (2 x 3MB) 10676h E8190 2.
Errata Errata AW1. EFLAGS Discrepancy on Page Faults after a Translation Change Problem: This erratum is regarding the case where paging structures are modified to change a linear address from writable to non-writable without software performing an appropriate TLB invalidation.
Errata AW3. Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads Problem: When data of Store to WT memory is used by two subsequent loads of one thread and another thread performs cacheable write to the same address the first load may get the data from external memory or L2 written by another core, while the second load will get the data straight from the WT Store. Implication: Software that uses WB to WT memory aliasing may violate proper store ordering.
Errata Violation #GP (General Protection Fault).
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW9. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware Problem: The MONITOR instruction is used to arm the address monitoring hardware for the subsequent MWAIT instruction. The hardware is triggered on subsequent memory store operations to the monitored address range.
Errata AW12. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the code streamwraps around in a way that one instruction ends at the last byte of the segment and the next instruction begins at 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system.
Errata AW15. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations. Problem: Under certain conditions as described in the Software Developers Manual section “Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW18. Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced.
Errata AW21. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered. 1) If an instruction that performs a memory load causes a code segment limit violation. 2) If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX) instruction that performs a memory load has a floating-point exception pending.
Errata b) RSM from an SMI during a HLT instruction. Implication: There may be a smaller than expected value in the INST_RETIRED performance monitoring counter. The extent to which this value is smaller than expected is determined by the frequency of the above cases. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW23. Returning to Real Mode from SMM with EFLAGS.
Errata will be left set in the in-service register and mask all interrupts at the same or lower priority. Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious vector should not be used when writing the LVT.
Errata The processor is in protected mode with paging enabled and the page global enable flag is set (PGE bit of CR4 register) G bit for the page table entry is set TLB entry is present in TLB when INIT occurs Implication: Software may encounter unexpected page fault or incorrect address translation due to a TLB entry erroneously left in TLB after INIT.
Errata Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
Errata Problem: CPUID leaf 0Ah reports the architectural performance monitoring version that is available in EAX[7:0]. Due to this erratum CPUID reports the supported version as 2 instead of 1. Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in comparison to which features are actually supported.
Errata Workaround: BIOS must leave the xTPR update transactions disabled (default). Status: For the steppings affected, see the Summary Tables of Changes. AW37. Performance Monitoring Event IA32_FIXED_CTR2 May Not Function Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio Problem: Performance Counter IA32_FIXED_CTR2 (MSR 30BH) event counts CPU reference clocks when the core is not in a halt state. This event is not affected by core frequency changes (e.g.
Errata Implication: This erratum has not been observed with commercially available software. Workaround: Although it is possible to have a single physical page mapped by two different linear addresses with different memory types, Intel has strongly discouraged this practice as it may lead to undefined results. Software that needs to implement memory aliasing should manage the memory type consistency. Status: For the steppings affected, see the Summary Tables of Changes. AW40.
Errata VM-execution control field above that of the TPR shadow while either of those bits is 1, incorrect behavior may result. This may lead to VMM software prematurely injecting an interrupt into a guest. Intel has not observed this erratum with any commercially available software. Workaround: VMM software raising the value of the TPR-threshold VM-execution control field should compare it to the TPR shadow.
Errata should (1) save from the VMCS (using VMREAD) the value of RIP before any VM entry to the wait-for SIPI state; and (2) restore to the VMCS (using VMWRITE) that value before the next VM entry that resumes the guest in any state other than wait-for-SIPI. Status: For the steppings affected, see the Summary Tables of Changes. AW44.
Errata Problem: If instructions from at least three different ways in the same instruction cache set exist in the pipeline combined with some rare internal state, selfmodifying code (SMC) or cross-modifying code may not be detected and/or handled. Implication: An instruction that should be overwritten by another instruction while in the processor pipeline may not be detected/modified, and could retire without detection. Alternatively the instruction may cause a Machine Check Exception.
Errata Problem: RSM instruction execution, under certain conditions triggered by a complex sequence of internal processor micro-architectural events, may lead to processor hang, or unexpected instruction execution results. Implication: In the above sequence, the processor may live lock or hang, or RSM instruction may restart the interrupted processor context through a nondeterministic EIP offset in the code segment, resulting in unexpected instruction execution, unexpected exceptions or system hang.
Errata [r/e]BP instructions without having an invalid stack during interrupt handling. However, an enabled debug breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is followed by an instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an unexpected instruction boundary since the MOV SS/POP SS and the following instruction should be executed atomically.
Errata Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the enable bit in the IA32_MC1_CTL MSR at the time of the last update. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW55.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AW57. IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected.
Errata Implication: In the event of a thermal event while a processor is waking up from Intel Deep Power-Down State, the processor will initiate an appropriate throttle response. However, the associated thermal interrupt generated may be lost. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW60. VM Entry May Fail When Attempting to Set IA32_DEBUGCTL.
Errata the PECI hold-off indication by keeping the PECI bus high when the PECI host sends the first bit of the address timing negotiation phase. If the PECI host does not choose to complete the transaction, it should consider the transaction a failure and retry 1ms after the processor deactivates the holdoff indication. Status: For the steppings affected, see the Summary Tables of Changes. AW62.
Errata AW65. Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM Entry Problem: If a VMM is using global page entries (CR4.PGE is enabled and any present page-directories or page-table entries are marked global), then on a VM entry, the instruction TLB (Translation Lookaside Buffer) entries caching global page translations of the VMM may not be invalidated.
Errata AW68. INIT Incorrectly Resets IA32_LSTAR MSR Problem: In response to an INIT reset initiated either via the INIT# pin or an IPI (Inter Processor Interrupt), the processor should leave MSR values unchanged. Due to this erratum IA32_LSTAR MSR (C0000082H), which is used by the iA32e SYSCALL instruction, is being cleared by an INIT reset.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW71. The XRSTOR Instruction May Fail to Cause a General-Protection Exception Problem: The XFEATURE_ENABLED_MASK register (XCR0) bits [63:9] are reserved and must be 0; consequently, the XRSTOR instruction should cause a generalprotection exception if any of the corresponding bits in the XSTATE_BV field in the header of the XSAVE/XRSTOR area is set to 1.
Errata Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE context only, may not follow program order and may execute before older stores. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW74.
Errata AW76. A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E or PDPTE Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set.
Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents: Intel® Core™2 Duo Processor E8000 and E7000 Series Datasheet Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B, 3A, and 3B All Specification Changes will be incorporated into a future version of the appropriate processor documentation.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: Intel® Core™2 Duo Processor E8000 and E7000 Series Datasheet Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B, 3A, and 3B All Specification Clarifications will be incorporated into a future version of the appropriate processor documentation. AW1. Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Section 10.
Documentation Changes Documentation Changes The Documentation Changes listed in this section apply to the following documents: Intel® Core™2 Duo Processor E8000 and E7000 Series Datasheet All Documentation Changes will be incorporated into a future version of the appropriate processor documentation.