Computer Accessories User Manual

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Intel ® 413808 and 413812 I/O Controllers in TPER Mode Developer’s Manual October 2007 Order Number: 317805-001US
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents—Intel® 413808 and 413812 Contents 1.0 Introduction............................................................................................................... 36 1.1 Design-in Considerations .................................................................................... 38 1.1.1 Software ............................................................................................... 39 1.2 Documentation References ............................................................................
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Intel® 413808 and 413812—Contents 2.3 2.4 2.5 2.6 2.7 2.2.6 Internal Bus Operation ............................................................................77 Big Endian Byte Swapping...................................................................................78 2.3.1 Inbound Byte Swapping...........................................................................78 2.3.2 Outbound Byte Swapping.........................................................................79 CompactPCI Hot-Swap ........
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Contents—Intel® 413808 and 413812 2.7.5.1 2.7.5.2 2.7.5.3 Master Aborts for Outbound Read or Write Request ..................... 109 Inbound Read Completion or Inbound Configuration Write Completion Message110 Master-Aborts Signaled by the ATU as a Target........................... 110 2.7.5.3.1 2.7.5.3.2 Uncorrectable Address Errors ...........................................110 Internal Bus Master-Abort ................................................. 110 2.7.6.3.1 2.7.6.3.2 2.7.6.3.
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Intel® 413808 and 413812—Contents 2.14.8 ATU Class Code Register - ATUCCR ......................................................... 151 2.14.9 ATU Cacheline Size Register - ATUCLSR ................................................... 152 2.14.10ATU Latency Timer Register - ATULT ....................................................... 152 2.14.11ATU Header Type Register - ATUHTR....................................................... 153 2.14.12ATU BIST Register - ATUBISTR ....................................
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Contents—Intel® 413808 and 413812 2.14.63HS_CNTRL - Hot-Swap Control/Status Register ........................................ 202 2.14.64Inbound ATU Base Address Register 3 - IABAR3 ....................................... 204 2.14.65Inbound ATU Upper Base Address Register 3 - IAUBAR3 ............................ 205 2.14.66Inbound ATU Limit Register 3 - IALR3 ..................................................... 206 2.14.67Inbound ATU Translate Value Register 3 - IATVR3 ....................................
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Intel® 413808 and 413812—Contents 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.3.5.1 Outbound Configuration Cycle Error Conditions............................ 253 3.3.5.2 Outbound Configuration Completions with Retry Status (CRS) .......253 3.3.5.3 Outbound PCI Express Message Transactions .............................. 254 3.3.5.4 Completion Timeout Mechanism ................................................ 254 Big Endian Byte Swapping...............................................
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Contents—Intel® 413808 and 413812 3.17.5 ATU Command Register - ATUCMD ......................................................... 298 3.17.6 ATU Status Register - ATUSR ................................................................. 299 3.17.7 ATU Revision ID Register - ATURID......................................................... 300 3.17.8 ATU Class Code Register - ATUCCR......................................................... 300 3.17.9 ATU Cacheline Size Register - ATUCLSR..........................
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Intel® 413808 and 413812—Contents 3.17.60PCI Express Device Status Register - PE_DSTS ......................................... 346 3.17.61PCI Express Link Capabilities Register - PE_LCAP ...................................... 347 3.17.62PCI Express Link Control Register - PE_LCTL ............................................ 348 3.17.63PCI Express Link Status Register - PE_LSTS .............................................349 3.17.64PCI Express Slot Capabilities Register - PE_SCAP .........................
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Contents—Intel® 413808 and 413812 3.17.111Outbound Vendor Message Header Register 1 - OVMHR1.......................... 389 3.17.112Outbound Vendor Message Header Register 2 - OVMHR2.......................... 390 3.17.113Outbound Vendor Message Header Register 3 - OVMHR3.......................... 390 3.17.114Outbound Vendor Message Payload Register - OVMPR.............................. 391 3.17.115PCI Interface Error Control and Status Register - PIE_CSR ....................... 392 3.17.
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Intel® 413808 and 413812—Contents 4.7.26 MSI-X Capability Identifier Register - MSI-X_Cap_ID ................................. 435 4.7.27 MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr..........................436 4.7.28 MSI-X Message Control Register - MSI-X_MCR..........................................437 4.7.29 MSI-X Table Offset Register — MSI-X_Table_Offset ................................... 438 4.7.30 MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset...................... 439 4.7.
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Contents—Intel® 413808 and 413812 7.1 7.2 Overview ....................................................................................................... 485 Theory of Operation......................................................................................... 486 7.2.1 System Controller ................................................................................ 486 7.2.2 Internal Bus Requester IDs.................................................................... 487 7.2.3 Parity Testing ...
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Intel® 413808 and 413812—Contents 8.3.3 Error Correction and Detection ............................................................... 519 8.3.3.1 ECC Generation....................................................................... 520 8.3.3.2 ECC Generation for Partial Writes .............................................. 521 8.3.3.3 ECC Checking ......................................................................... 522 8.3.3.4 Scrubbing ................................................................
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Contents—Intel® 413808 and 413812 10.1 Overview ....................................................................................................... 565 10.2 Theory of Operation......................................................................................... 566 10.2.1 Interrupt Controller Unit........................................................................ 566 10.3 The Intel XScale® Processor Exceptions Architecture............................................ 567 10.3.1 CPSR and SPSR...
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Intel® 413808 and 413812—Contents 10.7.26Interrupt Priority Register 1 — IPR1 ........................................................ 620 10.7.27Interrupt Priority Register 2 — IPR2 ........................................................ 621 10.7.28Interrupt Priority Register 3 — IPR3 ........................................................ 622 10.7.29Interrupt Priority Register 4 — IPR4 ........................................................ 623 10.7.30Interrupt Priority Register 5 — IPR5 .............
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Contents—Intel® 413808 and 413812 12.4.6 SMBus Controller ADDR0 Register Number — SM_ADDR0 .......................... 657 12.4.7 SMBus Controller Data Register — SM_DATA............................................ 658 12.4.8 SMBus Controller Status Register — SM_STS ........................................... 658 13.0 UARTs..................................................................................................................... 659 13.1 Overview ..................................................
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Intel® 413808 and 413812—Contents 14.4 Slave Mode Programming Examples ................................................................... 708 14.4.1 Initialize Unit ....................................................................................... 708 14.4.2 Write 1 Byte as a Slave ......................................................................... 708 14.4.3 Read 2 Bytes as a Slave ........................................................................708 14.5 Master Programming Examples.....
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Contents—Intel® 413808 and 413812 16.5.7.3 Threshold Events .................................................................... 758 16.5.7.4 PCI Interface Events ............................................................... 759 16.5.7.5 PCI Express Interface Events.................................................... 760 16.5.7.6 North Internal Bus Events ........................................................ 761 16.5.7.7 South Internal Bus Events........................................................
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Intel® 413808 and 413812—Contents 18.2.2.15Exit2-IR State......................................................................... 789 18.2.2.16Update-IR State...................................................................... 789 18.2.3 TAP Controller Registers ........................................................................790 18.2.3.1 Instruction Register ................................................................. 790 18.2.3.2 Instructions ...............................................
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Contents—Intel® 413808 and 413812 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 TPER Architecture Overview ...................................................................................... 37 Intel® 413808 and 413812 I/O Controllers in TPER Mode Functional Block Diagram .......... 43 ATU Block Diagram ..........................................................................................
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Intel® 413808 and 413812—Contents 54 4138xx SGPIO Unit 1 Pin Mapping ............................................................................ 473 55 Typical Internal Bus System Controller Block Diagram ................................................. 488 56 Intel® 413808 and 413812 I/O Controllers in TPER Mode SRAM Memory Controller Block Diagram513 57 ECC Write Flow ......................................................................................................
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Contents—Intel® 413808 and 413812 105 General Call Address .............................................................................................. 707 106 Example Block Diagram of Component with Counter ................................................... 729 107 Conceptual Diagram of Counter Array ....................................................................... 730 108 Example Block Diagram of Single PMON Counter .......................................................
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Intel® 413808 and 413812—Contents Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Intel® 413808 and 413812 I/O Controllers in TPER Mode/Firmware Mapping ....................36 Documentation References ........................................................................................40 ATU Command Support .........................................................................................
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Contents—Intel® 413808 and 413812 54 ATU Maximum Latency Register - ATUMLAT ............................................................... 168 55 Inbound ATU Limit Register 0 - IALR0....................................................................... 169 56 Inbound ATU Translate Value Register 0 - IATVR0 ...................................................... 170 57 Inbound ATU Upper Translate Value Register 0 - IAUTVR0 ...........................................
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Intel® 413808 and 413812—Contents 109 PCI Interface Error Control and Status Register - PIECSR.............................................220 110 PCI Interface Error Address Register - PCIEAR............................................................ 221 111 PCI Interface Error Upper Address Register - PCIEUAR................................................. 222 112 PCI Interface Error Context Address Register - PCIECAR ..............................................
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Contents—Intel® 413808 and 413812 162 Expansion ROM Base Address Register -ERBAR .......................................................... 313 163 ATU Capabilities Pointer Register - ATU_Cap_Ptr ........................................................ 314 164 ATU Interrupt Line Register - ATUILR........................................................................ 315 165 ATU Interrupt Pin Register - ATUIPR .........................................................................
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Intel® 413808 and 413812—Contents 217 PCI Express Advanced Error Header Log - ADVERR_LOG1 ............................................ 361 218 PCI Express Advanced Error Header Log - ADVERR_LOG2 ............................................ 361 219 PCI Express Advanced Error Header Log - ADVERR_LOG3 ............................................ 362 220 Root Error Command Register - RERR_CMD ............................................................... 362 221 Root Error Status Register - RERR_SR ..........
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Contents—Intel® 413808 and 413812 272 Outbound Interrupt Status Register - OISR................................................................ 417 273 Outbound Interrupt Mask Register - OIMR ................................................................. 418 274 Inbound Reset Control and Status Register - IRCSR.................................................... 419 275 Outbound Reset Control and Status Register - ORCSR.................................................
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Intel® 413808 and 413812—Contents 327 SGPIO Vendor Specific Code Register x - SGVSCRx .....................................................483 328 SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x ......................................... 484 329 Intel® 413808 and 413812 I/O Controllers in TPER Mode Initiator IDs ........................... 487 330 Address and Data Parity Testing Initiator IDs .............................................................489 331 Data Parity Testing Completer IDs .....
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Contents—Intel® 413808 and 413812 382 Interrupt Controller Co-Processor Register Addresses.................................................. 581 383 Interrupt Base Register — INTBASE.......................................................................... 583 384 Interrupt Size Register — INTSIZE ........................................................................... 584 385 IRQ Interrupt Vector Register- IINTVEC ....................................................................
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Intel® 413808 and 413812—Contents 437 SMBus Controller ADDR2 Register — SM_ADDR2 ........................................................ 656 438 SMBus Controller ADDR1 Register Number — SM_ADDR1 ............................................ 657 439 SMBus Controller ADDR0 Register Number — SM_ADDR0 ............................................ 657 440 SMBus Controller Data Register — SM_DATA.............................................................. 658 441 SMBus Controller Status Register — SM_STS ......
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Contents—Intel® 413808 and 413812 492 PMON Command Register 0-7 - PMON_CMD[0:7]..................................................... 749 493 PMON Event Register 0-7 - PMON_EVR[0:7] ............................................................ 753 494 PMON Status Register 0-7 - PMON_STS[0:7] ........................................................... 754 495 PMON DATA Register 7-0 - PMON_DATA[7:0] .......................................................... 756 496 Event Selection Code Summary ................
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Intel® 413808 and 413812—Contents 545 Intel® 413808 and 413812 I/O Controllers ATUE Configuration Space Base Address Offset... 814 546 Address Translation Unit Registers — ATUE ................................................................815 547 Intel® 413808 and 413812 I/O Controllers in TPER Mode PCI Function Visibility.............. 819 548 Coprocessor Registers Assigned to Integrated Peripherals ............................................ 819 549 Coprocessor Register Locations .....................
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Contents—Intel® 413808 and 413812 Revision History Date Revision October 2007 001 October 2007 Order Number: 317805-001US Description Initial Release.
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Intel® 413808 and 413812—Introduction 1.0 Introduction Table 1. This document covers the Intel® 413808 and 413812 I/O Controllers (4138xx). Note that the 4138xx operates in multiple modes, depending on which mode, determines when this manual is applicable. (In part or whole) With 4138xx in I/O Controller Mode, the 4138xx is a stand-alone SAS/SATA I/O Controller, the host driver interface to the 4138xx is via SLI protocol through the TPMI1 unit.
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Introduction—Intel® 413808 and 413812 Figure 1. The overall high-level architecture is shown in Figure 1. TPER Architecture Overview Driver MU Application Core TPMI Transport Core SLI Host PTRs SLIM (BAR 0) SLI CMD Wings SLI RSP Wings SLI PORT PTRs Application Core Memory Transport Memory SRAM When the 4138xx is in TPER mode, the interface to the host driver is under the control of the Application Core, and as with the 81348, the MU provides the hardware for the messaging interface.
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Intel® 413808 and 413812—Introduction 1.1 Design-in Considerations • • • 81348 4138xx 81348 For In Place Upgrade, the SKU must be used. The SKU cannot be upgraded to full featured RAID. In place upgrade simply means using an SKU in IOC mode and then at some later point in time, updating the firmware and reset straps to put the into IOP mode. From the end user perspective it will appear as an in place upgrade from an I/O controller for a fully featured Intelligent RAID Subsystem.
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Introduction—Intel® 413808 and 413812 1.1.1 Software • PCI Configuration Space: For 4138xx in TPER mode (as with 81348), the PCI configuration space presented is that of the Address Translation Unit (ATU) and it is the responsibility of the Application Core firmware to setup things such as the device ID per their design.
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Intel® 413808 and 413812—Introduction 1.2 Documentation References Table 2. Documentation References For available documentation references please refer to the following URLs: http://developer.intel.com/design/storage/controller/docs/ioc340.htm http://developer.intel.com/design/iio/docs/iop348.htm Table 2 is a list of the available documentation for the 4138xx that is referenced for a TPER design.
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Introduction—Intel® 413808 and 413812 1.3 About This Document This document is the authoritative and definitive reference for the external architecture ® 413808 and 413812 I/O Controllers in TPER Mode (4138xx), with Intel of the Intel XScale® microarchitecture2. Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
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Intel® 413808 and 413812—Introduction 1.4 About the Intel® 413808 and 413812 I/O Controllers in TPER Mode The 4138xx is a single-function PCI devices that integrates two Intel XScale® processors with intelligent peripherals including a PCI bus application bridge and eight Serial-Attached SCSI (SAS) Engines. The SAS Engines on the 4138xx also support direct-attached Serial ATA (SATA) targets. The 4138xx also supports two internal busses: north internal bus and south internal bus.
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Introduction—Intel® 413808 and 413812 Figure 2. Figure 2 is a block diagram of the 4138xx.
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Intel® 413808 and 413812—Introduction 1.5 Intel® 413808 and 413812 I/O Controllers in TPER Mode Features The 81348 combines two Intel XScale® processors with powerful new features to create an intelligent I/O storage processor. This single- or multi-function PCI device is fully compliant with the PCI-X 2.0a and PCI Express 1.0a specifications.
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Introduction—Intel® 413808 and 413812 1.5.3 Internal Busses 1.5.4 Application DMA Controller 1.5.5 The 4138xx is architected around two internal busses: north internal bus and south internal bus. The two busses use the same bus protocol. The north internal bus is 128-bit wide and operates at speed up to 400 MHz. The south internal bus is 128-bits wide and operates at speeds up to 400 MHz. The south internal bus provides data paths for large DMA generated burst transactions.
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Intel® 413808 and 413812—Introduction 1.5.6 Messaging Unit 1.5.7 DDR Memory Controller 1.5.8 Peripheral Bus Interface 1.5.9 Performance Monitoring Unit 1.5.10 I2C Bus Interface Unit 1.5.11 UART Unit 1.5.12 Interrupt Controller Unit The Messaging Unit (MU) provides data transfer between the PCI system and the 4138xx. It uses interrupts to notify each system when new data arrives.
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Introduction—Intel® 413808 and 413812 1.5.13 Internal Bus System Controller 1.5.14 Inter-Processor Communication 1.5.15 Inter-Processor Messaging Unit 1.5.16 Timers 1.5.17 GPIO 1.5.18 FSENG Each internal bus (north and south) employs a internal System Controller. The internal System Controller observes all the address or data bus request from requestors and completors connected to the internal bus.
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Intel® 413808 and 413812—Introduction 1.6 Terminology and Conventions 1.6.1 Representing Numbers 1.6.2 Fields All numbers in this document can be assumed to be Base10 unless designated otherwise. In text, numbers in Base16 are represented as “nnnH”, where the “H” signifies hexadecimal. In pseudo code descriptions, hexadecimal numbers are represented in the form 0x1234ABCD. Binary numbers are not explicitly identified but are assumed when bit operations or bit ranges are used.
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Introduction—Intel® 413808 and 413812 1.6.3 Specifying Bit and Signal Values 1.6.4 Signal Name Conventions 1.6.5 Terminology The terms set and clear in this specification refer to bit values in register and data structures. When a bit is set, its value is 1; when the bit is clear, its value is 0. Likewise, setting a bit means giving it a value of 1 and clearing a bit means giving it a value of 0.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.0 Address Translation Unit (PCI-X) This chapter describes the operation modes, setup,®and implementation of the module which interfaces between the PCI bus and the Intel 413808 and 413812 I/O Controllers in TPER Mode (4138xx) internal bus. 2.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Figure 3. The 4138xx meets the standard requirements to be considered “Hot-Swap Silicon” detailed in the Compact PCI Hot-Swap Specification, Revision 2.1. Address and data are protected by byte-wise parity on the internal bus. The ATU includes four extended capability headers that implement Power Management capability as defined by the PCI Bus Power Management Interface Specification, Revision 1.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Figure 4.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.2 Note: ATU Address Translation The ATU allows PCI masters on the PCI ®bus to initiate transactions to the 4138xx internal bus and allows the Intel XScale processor (ARM* architecture compliant) to initiate transactions to the PCI bus. The ATU implements an address windowing scheme to determine which addresses to claim and translate to the destination bus. • The address windowing mechanism for inbound translation is described in Section 2.2.1.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 3. ATU Command Support PCI Command PCI Command Encoding Type 0001 0010 0011 0100 Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate 0000 1011 1100 1101 1110 1111 Notes: 1. 2. 3.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.2.1 Inbound Transactions Inbound transactions which target the ATU are translated and executed on the 4138xx internal bus. As a PCI target, the ATU is capable of accepting all PCI memory read and write operations as either a 32-bit or a 64-bit PCI target. In the conventional PCI mode Memory Write and Memory Write and Invalidate operations are performed as posted operations and all memory read operations are performed as delayed reads.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.2.1.1 Inbound Address Translation The ATU allows external PCI bus initiators to directly access the internal bus. These PCI bus initiators can read or write 4138xx memory-mapped registers or 4138xx local memory space. The process of inbound address translation involves two steps: 1. Address Detection. a. Determine when the 32-bit PCI address (64-bit PCI address during DACs) is within the address windows defined for the inbound ATU. b.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Figure 5. Figure 5 shows an example of inbound address detection. Inbound Address Detection Address is not claimed Base_Register Address is claimed PCI Address Space Inbound Translation Window Base_Register + Value of Limit_Register Address is not claimed B6322-01 Note: The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed with the associated inbound limit register.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Figure 6. Figure 6 shows an inbound translation example for 32-bit addressing. This example would hold true for an inbound transaction from PCI bus.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.2.1.2 Inbound Write Transaction An inbound write transaction is initiated by a PCI master and is targeted at either 4138xx local memory or a 4138xx memory-mapped register.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Data flow for the inbound write transaction on the internal bus is summarized as: • The ATU internal bus master requests the internal bus when IWADQ has at least one entry with associated data in the IWQ. • When the internal bus is granted, the internal bus master interface initiates the write transaction by driving the translated address onto the internal bus. For details on inbound address translation, see Section 2.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.2.1.3 Inbound Read Transaction An inbound read transaction is initiated by a PCI initiator and is targeted at either 4138xx local memory or a 4138xx memory-mapped register space. The read transaction is propagated through the inbound transaction queue (ITQ) and read data is returned through the inbound read queue (IRQ). When operating in the conventional PCI mode, all inbound read transactions are processed as delayed read transactions.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) • When operating in the PCI-X mode, once a split completion transaction has started, it continues until one of the following is true: — The requester (now the target) generates a Retry Termination, or a Disconnection at Next ADB (when the requester is a bridge) — The byte count is satisfied. — An internal bus Target Abort was detected.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 The data flow for an inbound read transaction on the internal bus is summarized in the following statements: • The ATU internal bus master interface requests the internal bus when a PCI address appears in an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU always uses conventional PCI ordering rules.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.2.1.4 Note: Inbound Configuration Cycle Translation The 4138xx ATU only accepts Type 0 configuration cycles with a function number of zero when bit[7] of the ATUHTR (see Section 2.14.11, “ATU Header Type Register ATUHTR” on page 153) is cleared or function numbers of zero and one when bit[7] of the ATUHTR is set. The ATU is configured through the PCI bus.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 ATU configuration address space starts at internal address 3100H. Therefore, P_AD[7:2] equal to 0000002 equates to address 3100H and P_AD[7:2] equal to 0000012 results in address 3104H and so on. For inbound configuration reads, IRQ and ITQ are used in the same manner as inbound memory read operations. The internal bus cycle that results are a 32-bit transaction.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.2.1.5 Discard Timers The ATU implements discard timers for inbound delayed transactions. These timers prevent deadlocks when10the initiator of a retried delayed transaction fails to complete the transaction within 2 or 215 PCI clock cycles on the initiating bus when operating in the conventional PCI mode.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.2.2 Outbound Transactions- Single Address Cycle (SAC) Internal Bus Transactions Outbound transactions initiated by the 4138xx core processor are directed to the PCI interface through the ATU. The core processor always generates Single Address Cycles on the internal bus.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.2.2.1 Outbound Address Translation - Internal Bus Transactions Figure 7. 4 Gbyte Section 0 of the Internal Bus Memory Map In addition to providing the mechanism for inbound translation, the ATU translates Intel XScale® processor-initiated cycles to the PCI bus. This is known as outbound address translation. Outbound transactions are processor or ADMA transactions targeted at the PCI bus.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.2.2.2 Figure 8. Outbound Address Translation Windows Inbound translation involves a programmable inbound translation window consisting of a base and limit register and a value register for PCI to internal bus translation. The outbound address translation windows use a similar methodology except that the outbound translation window limit sizes are fixed in the 4138xx internal bus address space; this removes the need for separate limit registers.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) ATU has four 4 Gbyte outbound memory translation windows and one 64 Kbyte outbound I/O translation window. By default, Outbound Memory Window 0 (OUMBAR0), Outbound Memory Window 1 (OUMBAR1), Outbound Memory Window 2 (OUMBAR2), and Outbound Memory Window 3 (OUMBAR3) reside in 4 Gbyte memory sections 1, 2, 3, and 4, respectively. The default location of the 64 KByte outbound I/O window range is from 0.FFFB.0000H to 0.FFFB.FFFFH.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 The translation portion of outbound ATU transactions is accomplished with a value register in the same manner as inbound translations. Each outbound memory window is associated with one translation register which provides the upper translation addresses (OUMWVR0-3). When the corresponding OUMWVRx register is all-zero a SAC transaction is generated on the PCI bus.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.2.3 Outbound Write Transaction An outbound write transaction is initiated by the Intel XScale® processor4 or by one of the ADMA channels and is targeted at a PCI target on the PCI bus. The outbound write address and write data are propagated from the 4138xx internal bus to a PCI bus through OWADQ and OWQ, respectively. The ATUs internal bus target interface claims the write transaction and forwards the write data through to the targeted PCI bus.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 The PCI interface is responsible for completing the outbound write transaction with the PCI address translated from the OWADQ and the data in the OWQ. The data flow for an outbound write transaction on the PCI bus is summarized in the following statements: • ATU PCI interface requests PCI bus, when completed internal bus transaction is in OWADQ and data associated with transfer in OWQ.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.2.4 Outbound Read Transaction An outbound read transaction is initiated by the Intel XScale® processor5 or an ADMA channel and is targeted at a PCI slave on the PCI bus. The read transaction is propagated through the outbound transaction queue (OTQ) and read data is returned through the outbound read queue (ORQ).
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.2.5 Note: 2.2.5.1 Outbound Configuration Cycle Translation Outbound ATU provides a port programming model for outbound configuration cycles. Performing an outbound configuration cycle to the PCI bus involves up to two internal bus cycles: 1. Writing Outbound Configuration Cycle Address Register (OCCAR) with PCI address used during configuration cycle. See the PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.2.5.2 PCI-X Mode 2 Considerations for Outbound Configuration Cycles 2.2.5.3 Outbound Configuration Cycle Error Conditions In addition to the PCI-X Mode 1 changes relative to Conventional PCI mode, for PCI-X Mode 2, the definition for bits 31:24 of the configuration address has changed.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.2.6 Internal Bus Operation Complete internal bus operation of the 4138xx is defined in Chapter 7.0, “System Controller (SC) and Internal Bus Bridge”. The ATU acts as both internal bus master and internal bus slave device.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.3.2 Note: Outbound Byte Swapping When enabled, the swapping occurs as described in Figure 11, “Outbound Byte Swapping for Transaction with Byte Count of 1” on page 79, Figure 12, “Outbound Byte Swapping for Transaction with Byte Count of 2” on page 79, and Figure 13, “Outbound Byte Swapping for Transaction with Byte Count of 3 or Larger” on page 79.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.4 CompactPCI Hot-Swap 2.4.1 Pin Interface Table 7. Compact PCI Hot-Swap The 4138xx meets the standard requirements to be considered “Hot-Swap Silicon” detailed in the Compact PCI Hot-Swap Specification, Revision 2.1. This includes a dedicated pin interface and extended capability header. Hot-Swap Control and Status Register is implemented via the Extended Capability Pointer mechanism in the ATUs configuration space (Section 2.14.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.4.1.1 Compact PCI Hot-Swap Mode Select HS_SM# must be asserted (0b) to enable Hot-Swap functionality. HS_FREQ[1:0] pins allow the 4138xx to determine the cPCI backplane operating frequency without needing to see a PCI-X initialization pattern. These pins are only valid when HS_SM# is sampled as 0b during P_RST#. Table 8.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.5 Expansion ROM Translation Unit The inbound ATU supports one address range (defined by a base/limit register pair) used for the Expansion ROM. Refer to the PCI Local Bus Specification, Revision 2.3 for details on Expansion ROM format and usage. During a powerup sequence, initialization code from Expansion ROM is executed once by the host processor to initialize the associated device. The code can be discarded once executed.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.6 ATU Queue Architecture ATU operation and performance depends on the queueing mechanism implemented between the internal bus interface and PCI bus interface. As indicated in Figure 4, the ATU queue architecture consists of separate inbound and outbound queues. The function of each queue is described in the following sections. 2.6.1 Inbound Queues Table 9.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.6.1.2 Inbound Read Queue Structure Table 10. Inbound Read Prefetch Data Sizes The inbound read queues are responsible for retrieving data from local memory and returning it to the PCI bus in response to a read transaction initiated from a PCI master. When operating in the conventional PCI mode, reads are handled as delayed transactions. When operating in the PCI-X mode reads are handled as split transactions.
PAGE 85
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.6.1.3 Inbound Delayed Write Queue The IDWQ is used specifically for inbound configuration write cycles to the ATU. I/O Write transactions are not accepted by the ATU and result in a Master Abort. The IDWQ contains both the address and data of a configuration write cycle. When operating in the conventional PCI mode, the configuration writes are handled as delayed writes.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.6.2 Outbound Queues Table 12. Outbound Queues The outbound queues of the ATU are used to hold read and write transactions from the core processor directed at the PCI bus. Each ATU outbound queue structure has a separate read queue, write queue, and address queue. Table 12 contains information about ATU outbound queues.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.6.3 Note: Table 13. Transaction Ordering Because the ATU can process multiple transactions, they must maintain proper ordering to avoid deadlock conditions and improve throughput. The ATU transaction ordering rules used by the 4138xx are listed in Table 13 for the inbound direction and Table 14 on page 88 for the outbound direction. The tables are based on the direction the transaction is moving, i.e.
PAGE 88
Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 14. ATU Outbound Data Flow Ordering Rules Row Pass Column? Outbound Posted Write Request Outbound Non-postedc Write Request Outbound Read Request Inbound Delayed Read Completion (DRC) Inbound Split Read Completion (SRC) Inbound Delayed Write Completion (DWC) Inbound Split Write Completion (SWC) a. b. c.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 These transaction ordering rules define the way idata moves in both directions through the ATU. In Table 13 and Table 14 a NO response in a box means that based on ordering rules, the current transaction (the row) can not pass the previous transaction (the column) under any circumstance.
PAGE 90
Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.6.3.1 Table 15. Transaction Ordering Summary Table 15 and Table 16, define transaction ordering in relation to token assignment of the priority mechanism (this is discussed in Section 2.6.3). These tables are read as follows: 1. As the transaction enters the head of the respective queue, the question in column 2 is asked. 2.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 16.
PAGE 92
Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.6.4 Note: 2.6.4.1 Byte Parity Checking and Generation The internal bus interface of the ATU supports byte-wise parity protection on the internal bus. This includes A_PARITY[4:0] and D_PARITY[15:0] on the address bus (A[35:0]) and the data bus (D[127:0]) respectively. For an outbound write request (or inbound read completion) the internal bus interface verifies the write request address parity and data parity on the data cycles.
PAGE 93
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.6.4.2 Parity Checking On an outbound request, address parity is checked on the address bus A[35:0]. The parity bits are checked by first bit XORing the address bits shown in Table 17 with the corresponding address parity bits, and then verifying when the result of each of the XORed operations is equal to zero. As an example, the parity calculation for the lowest order byte of the address bus A[7:0] is carried as follows: Equation 6.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7 ATU Error Conditions PCI and internal bus error conditions cause ATU state machines to exit normal operation and return to idle states. In addition, status bits are set to inform error handling code of exact cause of error condition. Error conditions and status can be found in the ATUSR.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.1 Note: Uncorrectable Address and Uncorrectable Attribute Errors on the PCI Interface The ATUs must detect and report uncorrectable address and attribute (PCI-X mode only) errors for transactions on the PCI bus.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.2 Note: Correctable Address and Correctable Attribute Errors on the PCI Interface In PCI-X Mode 2 (when single-bit correction is enabled), the ATUs must detect and report correctable address and attribute (PCI-X mode only) errors for transactions on the PCI bus.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.3 Uncorrectable Data Errors on the PCI Interface Two kinds of uncorrectable data errors can occur on the PCI interface: errors as an initiator and errors as a target.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.3.1 Outbound Read Request Uncorrectable Data Errors 2.7.3.1.1 Immediate Data Transfer As an initiator, the ATU may encounter this error condition in Conventional or PCI-X mode when the target transfers data immediately rather than signalling a Retry7 (Conventional Delayed Read Request) or a Split Response Termination (PCI-X Split Read Request).
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.3.1.2 Split Response Termination As an initiator, the ATU may encounter this error condition in PCI-X mode when the target signals a Split Response Termination. Parity errors occurring during Split Response Terminations of Read Requests by the ATU are recorded, PERR# is asserted (when enabled) and SERR# is asserted (when enabled).
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.3.2 Outbound Write Request Uncorrectable Data Errors 2.7.3.2.1 Outbound Writes that are not MSI (Message Signaled Interrupts) 2.7.3.2.2 As an initiator, the ATU may encounter this error condition when operating in either the Conventional or PCI-X modes. Uncorrectable Data Errors occurring during write operations initiated by the ATU may record the assertion of PERR# from the target on the PCI Bus.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.3.3 2.7.3.4 Inbound Read Completions Uncorrectable Data Errors As an initiator, ATU may encounter this error condition when operating in PCI-X mode. When as the completer of a Split Read Request the ATU observes PERR# assertion during the split completion transaction, the ATU attempts to complete the transaction normally and no further action are taken.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.3.7 Outbound Read Completion Uncorrectable Data Errors As a target, the ATU may encounter this error when operating in the PCI-X mode. Uncorrectable Data errors occurring during read completion transactions that are claimed by the ATU are recorded, PERR# is asserted (when enabled) and SERR# is asserted (when enabled).
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.3.8 Outbound Split Write Uncorrectable Data Error Message The ATU claims a Split Completion Error Message that indicates an uncorrectable data error has occurred on one of the ATUs non-posted (I/O or Configuration) write requests (Message Class = 2h, Message Index = 01h -- Uncorrectable Split Write Data Error or Message Class = 1h, Message Index = 02h --Uncorrectable Write Data Error).
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.3.9 Inbound Configuration Write Request 2.7.3.9.1 Conventional PCI Mode As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. To allow for correct data parity calculations for delayed write transactions, the ATU delays the assertion of STOP# (signalling a Retry) until PAR is driven by the master.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.3.9.2 PCI-X Mode Uncorrectable Data errors occurring during configuration write operations received by the ATU may cause PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error occurs, the ATU accepts the write data and complete with a Split Response Termination.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.3.10 Split Completion Messages As a target, the ATU may encounter this error when operating in the PCI-X mode. Uncorrectable Data errors occurring during Split Completion Messages claimed by the ATU may assert PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the ATU accepts the data and complete normally.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.4 Correctable Data Errors on the PCI Interface 2.7.4.1 Inbound Read Request Correctable Data Errors 2.7.4.1.1 Immediate Data Transfer When the 4138xx PCI interface is operating in Mode 2 and Single-Bit Correction is enabled, correctable data errors may occur on the PCI bus. Two kinds of correctable data errors can occur on the PCI interface: errors as an initiator and errors as a target.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.4.3 Outbound Read Completion Correctable Data Errors 2.7.4.4 Inbound Configuration Write Request 2.7.4.5 Split Completion Messages As a target device, when an outbound read completion correctable data error is detected, the following actions are taken: • The error is corrected and the ATU completes the transaction on the PCI bus as when no error had occurred. Then, the transaction is forwarded to the internal bus normally.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.5 Master Aborts on the PCI Interface 2.7.5.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.5.2 Inbound Read Completion or Inbound Configuration Write Completion Message The ATU encounters this error only in the PCI-X mode. A master abort is signaled when the target of the transaction does not assert DEVSEL# within 7 clocks of the assertion of FRAME#.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.6 Target Aborts on the PCI Interface 2.7.6.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.6.2 Inbound Read Completion or Inbound Configuration Write Completion Message The ATU encounters this error only in the PCI-X mode. A target abort is signaled when the target of the transaction simultaneously deasserts DEVSEL#, deasserts TRDY#, and asserts STOP#.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.7 Warning: 2.7.7.1 2.7.7.2 Corrupted or Unexpected Split Completions When any of the errors discussed in this section actually occur, a catastrophic system failure is likely to result from which the PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0 provides no recovery mechanism. In these cases, the ATU may be communicating with a non-compliant target device or the system may not be configured properly.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.8 Note: SERR# Assertion and Detection The ATU is capable of reporting error conditions through the use of the SERR# output. The following conditions may result in the assertion of SERR# by the ATU: • An uncorrectable address error (or an uncorrectable attribute error when operating in the PCI-X mode) is detected by the ATU PCI interface (see Section 2.7.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.9 Internal Bus Error Conditions 2.7.9.1 Master Abort on the Internal Bus 2.7.9.1.1 Inbound Write Request An internal bus error results in a bit being set ®in the Interrupt Status Registers at which time an interrupt is driven to the Intel XScale processor. Unlike PCI errors, internal bus error conditions are not maskable. The following sections detail internal bus error conditions for the ATU.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.9.1.2 Note: Inbound Read Request When operating in the Conventional mode, the following actions with the given constraints are performed by the ATU when a master abort is detected by the internal initiator interface during an inbound read transaction: • Set the Internal Bus Master Abort bit (bit 7) in the ATUISR • Return a target abort condition to the initiating master during the delayed completion cycle on the PCI bus.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.9.2 2.7.9.2.1 2.7.9.2.2 Note: Target Abort on the Internal Bus Target Aborts can be seen by the internal bus requester interface during inbound read operations to the memory controller. During inbound read operations, the memory controller is capable of signalling a target abort when a multi-bit, unrecoverable ECC error is encountered. This can occur during any read operation. Note target aborts are signalled on a Qword basis.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.7.9.3 Parity Error on the Internal Bus 2.7.9.3.1 Conventional Mode 2.7.9.3.2 PCI-X Mode Note: The 4138xx provides support for byte-wise parity protection on the internal bus. The internal bus consists of a 36 bit address bus and 128 bit data bus; both are protected by byte-wise parity. The internal bus parity protection is provided independent of the operating mode of the ATUs PCI interface.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.7.10 ATU Error Summary Table 18. ATU Error Reporting Summary - PCI Interface (Sheet 1 of 5) Table 18 summarizes the ATU error reporting for PCI bus errors and Table 19 summarizes the ATU error reporting for internal bus errors. The tables assume that all error reporting is enabled through the appropriate command registers (unless otherwise noted). The ATU Status Register records PCI bus errors.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 18.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 18.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 18.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 18. ATU Error Reporting Summary - PCI Interface (Sheet 5 of 5) Error Condition (Bus Modea) Inbound EROM Write Request Target-Abort (All) (All) Unexpected Split Completion (PCI-X) (PCI-X) a. b. c. d. e. Bits Set in ATU Status Register (ATUSRb) or Bits Set in Interrupt Mask Bit in PCI-X Status Register ATU Interrupt Status ATUIMR or ATUCR c (PCIXSR ) Register (ATUISR) and/or ECC Logging Registersd (ECCLOG) PCI Bus Error Response (i.e.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 19. ATU Error Reporting Summary - Internal Bus Interface Error Conditionab (Bus Mode ) Bits Set in Bits Set in Interrupt Mask Bit in ATU Status Register ATU Interrupt Status ATUIMR or ATUCR c (ATUSR ) Register (ATUISR) PCI Bus Error Response (i.e., signal Target-Abort, signal Master-Abort etc.) Inbound Write Request Master-Abort (All) Assert SERR#.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.8 Message-Signaled Interrupts The Messaging Unit is responsible for the generation of all of the Outbound Interrupts from the 4138xx. These interrupts can be delivered to the Host Processor via the P_INTA# output pin or the Message Signaled Interrupt (MSI) mechanism.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.9 Internal Interrupts The ATU has 3 internal interrupts that connect to the internal Interrupt Controller Unit.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.10 2.10.1 Vital Product Data Vital Product Data (VPD) provides detailed information to the system regarding the hardware, software and microcode elements of a device. This information may include Part Number, Serial Number or other detailed information. This information resides on a non-volatile storage device (i.e., Flash Memory) attached to the 4138xx.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.10.2 Accessing Vital Product Data 2.10.2.1 Reading Vital Product Data Warning: The VPD Capabilities List Item provides three fields which the system uses to access the Vital Product Data: VPD Address DWORD Aligned Byte address of the VPD to be accessed which is represented by VPDAR[14:0]. Note that this means that the maximum size of the VPD is 128 Kbytes. The user may pick any 128 Kbyte block of memory in the storage component for the VPD.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.10.2.2 Warning: Writing Vital Product Data Using the fields defined in the VPD Capabilities List Item, the 4138xx writes Vital Product Data using the following sequence of events: 1. Host processor executes a configuration write of the VPD data to be written to the VPDDR. 2. Host processor executes a configuration write of the VPD address to the VPDAR with the Flag set. 3.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.11 Multi-Function Support 2.11.1 PCI-X Interface Control Parameters Multiple functions are not supported for 4138xx. Note: Table 20. The following registers are located in the configuration space header and extended space and provide control of the PCI Interface. The effect of each bit is detailed below. Table 20 is referring to only enabled functions. In root complex mode multi-function is not applicable.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.11.2 PCI-X Interface Status Reporting Table 21. PCI-X Host Interface Status Reporting Usagea The following registers are located in the configuration space header and extended space and provide status (error conditions) of the PCI Interface.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.12 Central Resource Functionality 2.12.1 Multi-Function Support 2.12.2 Outbound Transactions 2.12.3 PCI Reset (P_RSTOUT#) 2.12.4 PCI Clock Outputs (P_CLKOUT, P_CLKO[3:0]) Warning: Central Resource is not supported on 4138xx. When operating as a central resource, the ATU behaves as a single function device and claims memory transactions only for the ATU function.
PAGE 133
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.12.5 External Clock Driver (CR_FREQ[1:0]) Table 22. CR_FREQ[1:0] Encoding When the internal PCI Clock outputs are not sufficient, an external clock driver can be used to supply additional PCI Clocks. To facilitate the use of an external driver, the CR_FREQ[1:0] pins are driven based on the settings in the PCI-X capability field (bits 19:16) in the “PCI Configuration and Status Register - PCSR”.
PAGE 134
Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.12.6 Bus Mode and Frequency Initialization Table 23. Device Mode/Frequency Capability Reporting The ATUs PCI Bus interface is capable of operating at a variety of frequencies, and in either Conventional PCI mode, or in PCI-X mode. The bus mode is established when coming out of the bus segment reset sequences.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 24 details the PCI bus frequency initialization as a function of the PCI Bus PCIXM1_100# and PCIXM2_100# reset strap, and the sampled secondary device capabilities when operating in PCI-X mode. Table 24. PCI Bus Frequency Initializationa P_PCIXCAP P_MODE 2 < 0.11VCC < 0.11VCC <0.6VCC & >0.11 VCC <0.6VCC & >0.11VCC -b - PCIXM2_1 PCI Bus P_M66EN PCIXM1_1 00# 00# Mode - - GND Ground Not connected - - - VCC - - GND <0.6VCC & >0.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 25 describes the bus mode and frequency initialization pattern that the ATU signals on its secondary bus when coming out of P_RST#, after having evaluated the above information. Table 25.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 When operating as an endpoint in Hot-Swap mode (HS_SM# = 0), PCSR[19:16] is set based on the HS_FREQ[1:0] pins. For more details see Table 8, “HS_FREQ Encoding” on page 81. Figure 14.
PAGE 138
Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.13 Embedded Bridge Functionality Note: Not supported for 4138xx.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14 2.14.1 Register Definitions Every PCI device implements its own separate configuration address space and configuration registers. The PCI Local Bus Specification, Revision 2.3 requires that configuration space be 256 bytes, and the first 64 bytes must adhere to a predefined header format. Figure 15 defines the header format. Table 26 shows the PCI configuration registers, listed by internal bus address offset.
PAGE 140
Intel® 413808 and 413812—Address Translation Unit (PCI-X) In the ATU Status Register (Section 2.14.6) the appropriate bit is set indicating that the Extended Capability Configuration space is supported. When this bit is read, the device can then read the Capabilities Pointer register (Section 2.14.22) to determine the configuration offset of the Extended Capabilities Configuration Header. The format of these headers are depicted in Figure 16, Figure 18, Figure 19, Figure 19 and Figure 21. Figure 16.
PAGE 141
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Following the Capability Identifier Register is the single byte Next Item Pointer Register (Section 4.7.27, “MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr”) which indicates the configuration offset of an additional Extended Capabilities Header, when supported. In the ATU, the Next Item Pointer Register is set to A0H indicating that there is an additional Extended Capabilities Headers supported in the ATUs configuration space. Figure 18.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Figure 20. ATU Extended Configuration Header Format (Compact PCI Hot-Swap Capability) Reserved Hot-Swap Ctrl/Status Next Item Pointer cPCI Capability ID E8H B6330-01 The first byte at the Extended Configuration Offset E8H is the Compact PCI Hot-Swap Capability Identifier Register (Section 2.14.61). This identifies this Extended Configuration Header space as the type defined by the Compact PCI Hot-Swap Specification, Revision 2.1.
PAGE 143
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.2 Note: Table 26. Internal Bus Registers A subset of the ATU registers are accessible through both inbound PCI configuration cycles and the 4138xx core CPU (Register offsets 000H through 0FFH). The balance of the registers are accessible only via the internal bus. Table 26, “Address Translation Unit Registers” on page 143 represents all of the ATU registers.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 26. Register Offset 048H 04CH 050H 054H 058H 05CH 060H 064H 068H 06CH 070H 074H 078H 07CH 080H — 08FH 090H 091H 092H 094H 098H 099H 09AH 09CH 0A0H 0A1H 0A2H 0A4H 0A8H 0ACH 0AEH 0B0H 0B1H 0B2H 0B4H 0B8H 0BCH — 0C8H 0CCH 0D0H 0D1H 0D2H 0D4H 0D8H 0DCH 0E0H 0E4H Address Translation Unit Registers (Sheet 2 of 3) ATU Register Section, Name, Page Section 2.14.30, “Inbound ATU Upper Translate Value Register 0 - IAUTVR0” on page 170 Section 2.14.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 26. Address Translation Unit Registers (Sheet 3 of 3) Register Offset ATU Register Section, Name, Page 0E8H Section 2.14.61, “CompactPCI Hot-Swap Capability ID Register” on page 200 0E9H Section 2.14.62, “Offset EDh: HS_NXTP - Next Item Pointer” on page 201 0EAH Section 2.14.63, “HS_CNTRL - Hot-Swap Control/Status Register” on page 202 0EBH Reserved 0ECH — 0FFH Reserved 100H — 1FFH Reserved 200H Section 2.14.
PAGE 146
Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 27. ATU Internal Bus Memory Mapped Register Range Offsets INTERFACE_SEL_PCIX# Asserted (0) Asserted (0) Deasserted (1) Deasserted (1) Table 28. CONTROLLER_ONLY# Internal Bus MMR Address Range Offset (Relative to PMMRBAR) Deasserted (1) Asserted (0) Asserted (0) Deasserted (1) +4 8000H +4 C000H +4 C000H +4 D000H PCI-X Pad Registers Register Offset 2100H 2104H 2108H 210CH Section, Register Name - Acronym (Page) Section 2.14.
PAGE 147
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.3 ATU Vendor ID Register - ATUVID Table 29. ATU Vendor ID Register - ATUVID ATU Vendor ID Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3.
PAGE 148
Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.5 ATU Command Register - ATUCMD Table 31. ATU Command Register - ATUCMD ATU Command Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3 and in most cases, affect the behavior of the PCI ATU and devices on the PCI bus.
PAGE 149
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.6 ATU Status Register - ATUSR Table 32. ATU Status Register - ATUSR (Sheet 1 of 2) The ATU Status Register bits adhere to the PCI Local Bus Specification, Revision 2.3 definitions. The read/clear bits can only be set by internal hardware and cleared by either a reset condition or by writing a 12 to the register.
PAGE 150
Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 32.
PAGE 151
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.7 ATU Revision ID Register - ATURID Table 33. ATU Revision ID Register - ATURID Revision ID Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3.
PAGE 152
Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.9 ATU Cacheline Size Register - ATUCLSR Table 35. ATU Cacheline Size Register - ATUCLSR Cacheline Size Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register is programmed with the system cacheline size in DWORDs (32-bit words). Cacheline Size is restricted to either 0, 8 or 16 DWORDs; the ATU interprets any other value as “0”.
PAGE 153
Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.11 ATU Header Type Register - ATUHTR Header Type Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register indicates the layout of ATU configuration space bytes 10H to 3FH. The MSB indicates whether or not the device is multi-function. Table 37.
PAGE 154
Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.12 ATU BIST Register - ATUBISTR The ATU BIST Register controls the functions the Intel XScale® processor performs when BIST is initiated. This register is the interface between the host processor requesting BIST functions and the 4138xx replying with the results from the software implementation of the BIST functionality. Table 38.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.13 Inbound ATU Base Address Register 0 - IABAR0 The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) defines the block of memory addresses where the inbound translation window 0 begins. The inbound ATU decodes and forwards the bus request to the 4138xx internal bus with a translated address to map into 4138xx local memory.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.14 Inbound ATU Upper Base Address Register 0 - IAUBAR0 This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.15 Inbound ATU Base Address Register 1 - IABAR1 The Inbound ATU Base Address Register 1 (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) defines the block of memory addresses where the inbound translation window 1 begins. The inbound ATU decodes and forwards the bus request to the 4138xx internal bus with a translated address to map into 4138xx local memory.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.16 Inbound ATU Upper Base Address Register 1 - IAUBAR1 This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.17 Inbound ATU Base Address Register 2 - IABAR2 The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) defines the block of memory space addresses where the inbound translation window 2 begins. The inbound ATU decodes and forwards the bus request to the 4138xx internal bus with a translated address to map into 4138xx local memory.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.18 Inbound ATU Upper Base Address Register 2 - IAUBAR2 This register contains the upper base address when decoding PCI addresses for memory space (Memory Space Indicator in IABAR2 is clear) beyond 4 GBytes. Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.19 ATU Subsystem Vendor ID Register - ASVIR ATU Subsystem Vendor ID Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. Table 45.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.21 Expansion ROM Base Address Register - ERBAR The Expansion ROM Base Address Register defines the block of memory addresses used for containing the Expansion ROM. It permits the inclusion of multiple code images, allowing the device to be initialized. The code image supplied consists of either executable code or an interpreted code. Each code image must start on a 512 byte boundary and each must contain the PCI Expansion ROM header.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.22 ATU Capabilities Pointer Register - ATU_Cap_Ptr The Capabilities Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register provides an offset in this function’s PCI Configuration Space for the location of the first item in the first Capability list.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.23 Determining Block Sizes for Base Address Registers Note: Table 49. The required address size and type can be determined by writing ones to a base address register and reading from the registers. By scanning the returned value from the least-significant bit of the base address registers upwards, the programmer can determine the required address space size.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 50.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.24 ATU Interrupt Line Register - ATUILR ATU Interrupt Line Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register identifies the system interrupt controller's interrupt request lines which connect to the device's PCI interrupt request lines (as specified in the interrupt pin register).
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.25 ATU Interrupt Pin Register - ATUIPR ATU Interrupt Pin Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register identifies the interrupt pin the ATU and Messaging Unit interface uses. The 4138xx is, a PCI single-function device and, as such, generates only one interrupt output. The interrupt output is for the Messaging Unit on INTA#. Table 52.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.27 ATU Maximum Latency Register - ATUMLAT ATU Maximum Latency Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register specifies how often the device needs to access the PCI bus in increments of 8 PCI clocks.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.28 Inbound ATU Limit Register 0 - IALR0 Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI bus (originated from the PCI bus) to the 4138xx internal bus. The address translation block converts PCI addresses to internal bus addresses. The inbound translation base address for inbound window 0 is specified in Section 2.14.13. When determining block size requirements — as described in Section 2.14.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.29 Inbound ATU Translate Value Register 0 - IATVR0 The Inbound ATU Translate Value Register 0 (IATVR0) in conjunction with the “Inbound ATU Upper Translate Value Register 0 - IAUTVR0” on page 170 contain bits 35 to 12 of the internal bus address used to convert PCI bus addresses. The converted address is driven on the internal bus as a result of the inbound ATU address translation. Table 56.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.31 Inbound ATU Limit Register 1 - IALR1 Inbound address translation for memory window 1 occurs for data transfers occurring from the PCI bus (originated from the PCI bus) to the 4138xx internal bus. The address translation block converts PCI addresses to internal bus addresses. The inbound translation base address for inbound window 1 is specified in Section 2.14.15. When determining block size requirements — as described in Section 2.14.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.32 Inbound ATU Translate Value Register 1 - IATVR1 The Inbound ATU Translate Value Register 1 (IATVR1) in conjunction with the “Inbound ATU Upper Translate Value Register 1 - IAUTVR1” on page 172 contain bits 35 to 12 of the internal bus address used to convert PCI bus addresses. The converted address is driven on the internal bus as a result of the Inbound ATU address translation. Table 59.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.34 Inbound ATU Limit Register 2 - IALR2 Inbound address translation for inbound window 2 occurs for data transfers occurring from the PCI bus (originated from the PCI bus) to the 4138xx internal bus. The address translation block converts PCI addresses to internal bus addresses. The inbound translation base address for inbound window 2 is specified in Section 2.14.17. When determining block size requirements — as described in Section 2.14.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.35 Inbound ATU Translate Value Register 2 - IATVR2 The Inbound ATU Translate Value Register 2 (IATVR2) in conjunction with the “Inbound ATU Upper Translate Value Register 2 - IAUTVR2” on page 174 contain bits 35 to 12 of the internal bus address used to convert PCI bus addresses. The converted address is driven on the internal bus as a result of the Inbound ATU address translation. Table 62.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.37 Expansion ROM Limit Register - ERLR The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines as Expansion ROM address space. Block size is programmed by writing a value into the ERLR. Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one to one correspondence.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.38 Expansion ROM Translate Value Register - ERTVR The Expansion ROM Translate Value Register 0 (ERTVR) in conjunction with the “Expansion ROM Upper Translate Value Register - ERUTVR” on page 176 contain bits 35 to 12 of the internal bus address used to convert PCI bus addresses. The converted address is driven on the internal bus as a result of the Expansion ROM address translation. Table 65.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.40 ATU Configuration Register - ATUCR The ATU Configuration Register controls the outbound address translation for address translation unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard timer status, P_SERR# manual assertion, P_SERR# detection interrupt masking, and ATU BIST interrupt enabling. Table 67.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.41 PCI Configuration and Status Register - PCSR The PCI Configuration and Status Register has additional bits for controlling and monitoring various features of the PCI bus interface. Table 68.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 68.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 68.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.42 ATU Interrupt Status Register - ATUISR The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit of the 4138xx. All bits in this register are Read/Clear.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 69.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.43 ATU Interrupt Mask Register - ATUIMR The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts generated by the ATU. Table 70.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 70.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.44 VPD Capability Identifier Register - VPD_Cap_ID The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended Capability contained in that header. In the case of the 4138xx, this is the VPD extended capability with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. Table 71.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.46 VPD Address Register - VPDAR The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be accessed. The register is read/write and the initial value at power-up is indeterminate. A PCI Configuration Write to the VPDAR interrupts the Intel XScale® processor.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.48 PM Capability Identifier Register - PM_Cap_ID The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended Capability contained in that header.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.50 ATU Power Management Capabilities Register - APMCR Table 77. Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides information on the capabilities of the ATU function related to power management.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.51 ATU Power Management Control/Status Register - APMCSR Table 78. Power Management Control/Status bits adhere to the definitions in the PCI Bus Power Management Interface Specification, Revision 1.1. This 16-bit register is the control and status interface for the power management extended capability.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.52 ATU Scratch Pad Register - ATUSPR This register can be used for application specific purposes and has no direct impact on the hardware. Table 79.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.54 PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register describes the location of the next item in the function’s capability list. Table 81.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 82.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.56 PCI-X Status Register - PCIXSR This register identifies the capabilities and current operating mode of ATU when operating in the PCI-X mode. Table 83.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 83.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.57 ECC Control and Status Register - ECCCSR The ECCCSR register provides additional information about ECC errors that occurred on the PCI bus. Registers that store information from the failing transaction always store information directly from the PCI bus (uncorrected), even when correction of the error is possible.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) Table 84.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 84.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.58 ECC First Address Register - ECCFAR When the ECC Error Phase register (bits 6:4 of the ECCCSR) is non-zero (indicating that an error has been captured), the ECCFAR register indicates the contents of the P_AD[31:0] bus (for 64- and 32-bit buses) for the address phase of the transaction that included the error. For Dual Address Cycle (DAC) transactions, this represents the least significant 32-bits of the 64-bit address.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.59 ECC Second Address Register - ECCSAR When the ECC Error Phase register (bits 6:4 of the ECCCSR) is non-zero (indicating that an error has been captured) and the failing transaction included a dual address cycle (DAC), the ECCSAR register indicates the contents of the P_AD[31:0] bus (for 64- and 32-bit buses) for the second address phase of the transaction that included the error.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.60 ECC Attribute Register - ECCAR When the ECC Error Phase register (bits 6:4 of the ECCCSR) is non-zero (indicating that an error has been captured), the ECCAR register indicates the contents of the P_AD[31:0] bus (for 64- and 32-bit buses) for the attribute phase of the transaction that included the error. When the ECC Error Phase register is zero, the contents of this register are undefined.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.62 Offset EDh: HS_NXTP - Next Item Pointer Warning: Table 89. By default, the CompactPCI capability is the last capabilities list for the 4138xx, thus this register defaults to 00H. However, this register may be written to 90H prior to host configuration to include the VPD capability located at off-set 90H. Writing this register to any value other than 00H (default) or 90H is not supported and may produce unpredictable system behavior.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.63 HS_CNTRL - Hot-Swap Control/Status Register The 4138xx meets the standard requirements to be considered “Hot-Swap Silicon” detailed in the Compact PCI Hot-Swap Specification, Revision 2.1. Refer to the Compact PCI Hot-Swap Specification, Revision 2.1 for more details on the insertion and extraction processes. Table 90.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 Table 90.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.64 Inbound ATU Base Address Register 3 - IABAR3 The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block of memory addresses where the inbound translation window 3 begins. The inbound ATU decodes and forwards the bus request to the 4138xx internal bus with a translated address to map into 4138xx local memory.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.65 Inbound ATU Upper Base Address Register 3 - IAUBAR3 This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.66 Inbound ATU Limit Register 3 - IALR3 Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI bus (originated from the PCI bus) to the 4138xx internal bus. The address translation block converts PCI addresses to internal bus addresses. The inbound translation base address for inbound window 3 is specified in Section 2.14.17. When determining block size requirements — as described in Section 2.14.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.67 Inbound ATU Translate Value Register 3 - IATVR3 The Inbound ATU Translate Value Register 3 (IATVR3) in conjunction with the “Inbound ATU Upper Translate Value Register 3 - IAUTVR3” on page 207 contain bits 35 to 12 of the internal bus address used to convert PCI bus addresses. The converted address is driven on the internal bus as a result of the inbound ATU address translation. Table 94.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.69 Outbound I/O Base Address Register - OIOBAR The OIOBAR register locates the 64 KB I/O cycle address window in the 4138xx’s 64 Gbyte internal address space. When A[35:16] of the internal bus address matches the value in OIOBAR, the ATU claims the transaction and forward it over to the PCI interface as an I/O cycle.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.70 Outbound I/O Window Translate Value Register - OIOWTVR The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a result of the outbound ATU address translation. See Section 2.2.2.1, “Outbound Address Translation - Internal Bus Transactions” on page 68 for details on outbound address translation.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.71 Outbound Upper Memory Window Base Address Register 0 OUMBAR0 The OUMBAR0 register locates Outbound Memory Window 0 in a 4 Gbyte Memory section in the 4138xx 64 Gbyte internal address space. When A[35:32] of the internal bus address matches the value in OUMBAR0[3:0], the ATU claims the transaction and forward it over to the PCI interface. In translating the internal bus address A[35:0], A[31:0] is forwarded over to the PCI bus unmodified.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.72 Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to directly address anywhere within the 64-bit host address space. When this register is all-zero, then a SAC is generated on the PCI bus. Table 99.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.73 Outbound Upper Memory Window Base Address Register 1 OUMBAR1 The OUMBAR1 register locates Outbound Memory Window 1 in a 4 Gbyte Memory section in the 4138xx 64 Gbyte internal address space. When A[35:32] of the internal bus address matches the value in OUMBAR1[3:0], the ATU claims the transaction and forward it over to the PCI interface. In translating the internal bus address A[35:0], A[31:0] is forwarded over to the PCI bus unmodified.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.74 Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to directly address anywhere within the 64-bit host address space. When this register is all-zero, then a SAC is generated on the PCI bus. Table 101.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.75 Outbound Upper Memory Window Base Address Register 2 OUMBAR2 The OUMBAR2 register locates Outbound Memory Window 2 in a 4 Gbyte Memory section in the 4138xx 64 Gbyte internal address space. When A[35:32] of the internal bus address matches the value in OUMBAR2[3:0], the ATU claims the transaction and forward it over to the PCI interface. In translating the internal bus address A[35:0], A[31:0] is forwarded over to the PCI bus unmodified.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.76 Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2 The Outbound Upper 32-bit Memory Window Translate Value Register 2 (OUMWTVR2) defines the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to directly address anywhere within the 64-bit host address space. When this register is all-zero, then a SAC is generated on the PCI bus. Table 103.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.77 Outbound Upper Memory Window Base Address Register 3 OUMBAR3 The OUMBAR3 register locates Outbound Memory Window 3 in a 4 Gbyte Memory section in the 4138xx 64 Gbyte internal address space. When A[35:32] of the internal bus address matches the value in OUMBAR3[3:0], the ATU claims the transaction and forward it over to the PCI interface. In translating the internal bus address A[35:0], A[31:0] is forwarded over to the PCI bus unmodified.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.78 Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3 The Outbound Upper 32-bit Memory Window Translate Value Register 3 (OUMWTVR3) defines the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to directly address anywhere within the 64-bit host address space. When this register is all-zero, then a SAC is generated on the PCI bus. Table 105.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.79 Outbound Configuration Cycle Address Register - OCCAR The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration cycle address. The Intel XScale® processor writes the PCI configuration® cycles address, which enables outbound configuration read or write.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.80 Outbound Configuration Cycle Data Register - OCCDR The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write on the PCI bus. The register is logical rather than physical meaning that it is an address not a register. The Intel XScale® processor reads or writes the data registers memory-mapped address to initiate the configuration cycle on the PCI bus with the address found in the OCCAR.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.82 PCI Interface Error Control and Status Register - PIECSR This register indicates whether or not the ATU has detected and logged a PCI interface error. The register is also used to enabled the logging of additional errors. For more details, see Section 2.7, “ATU Error Conditions” on page 94.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.83 PCI Interface Error Address Register - PCIEAR When PCIECSR bit 0 is set, this register represents the lower 32-bits of the address for the error detected on the PCI Bus. Note that for a DAC cycle the address may be 64-bit. This register is used in conjunction with Section 2.14.84, “PCI Interface Error Upper Address Register - PCIEUAR” on page 222 in order to interpret the entire 64-bit PCI address for the error.
PAGE 222
Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.84 PCI Interface Error Upper Address Register - PCIEUAR When PCIECSR bit 0 is set and the PCI error detected included a DAC cycle, this register represents the upper 32-bit address of where the error was detected on the PCI bus. This register is used in conjunction with the Section 2.14.83, “PCI Interface Error Address Register - PCIEAR” on page 221. One error can be detected and logged.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.85 PCI Interface Error Context Address Register — PCIECAR When PCIECSR bit 0 is set, this register contains the DMA Channel Number and bits 30 through 5 of the address of the ADMA descriptor associated with the error detected on the PCI Bus.One error can be detected and logged. The software knows which ADMA descriptor context had the error by reading this register and decoding the contents of the PCIECSR. For error details, see Section 2.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.86 Internal Arbiter Control Register - IACR The Internal Arbiter Control Register is used to control which priority ring different PCI bus requesters (including the ATU) use. In addition, the method by which the arbiter parks on masters is configurable in this register. Table 113.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.87 Multi-Transaction Timer - MTT This register controls the amount of time that the 4138xx arbiter allows a PCI initiator to perform multiple back-to-back transactions on the PCI bus. The number of clocks programmed in the MTT represents the insured time slice (measured in PCI clocks) allotted to the current agent, after which the arbiter grants another agent that is requesting the bus. Table 114.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.88 PCIX RCOMP Control Register — PRCR In Central Resource mode this register can only be accessed when PCSR bit 21 is cleared. Refer to Table 68, “PCI Configuration and Status Register - PCSR” on page 178. Warning: Table 115.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.89 PCIX Pad ODT Drive Strength Manual Override Values Registers — PPODSMOVR In Central Resource mode this register can only be accessed when PCSR bit 21 is cleared. Refer to Table 68, “PCI Configuration and Status Register - PCSR” on page 178. Warning: Table 116.
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Intel® 413808 and 413812—Address Translation Unit (PCI-X) 2.14.90 PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V/1.5 V Switch Supply Voltage) — PPDSMOVR3.3_1.5 In Central Resource mode this register can only be accessed when PCSR bit 21 is cleared. Refer to Table 68, “PCI Configuration and Status Register - PCSR” on page 178. Warning: Table 117. PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3V/1.5V Switch Supply Voltage) — PPDSMOVR3.3_1.
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Address Translation Unit (PCI-X)—Intel® 413808 and 413812 2.14.91 PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated Supply Voltage) — PPDSMOVR3.3 In Central Resource mode this register can only be accessed when PCSR bit 21 is cleared. Refer to Table 68, “PCI Configuration and Status Register - PCSR” on page 178. Warning: Table 118. PCIX PAD DRIVE STRENGTH Manual Override Values Register (3.3 V Dedicated Supply Voltage) — PPDSMOVR3.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.0 Address Translation Unit (PCI Express) This chapter describes the operation modes, setup, and implementation of the module which interfaces between the PCI Express Link and the Intel® 413808 and 413812 I/O Controllers (4138xx) internal bus. 3.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 The ATU includes four capability headers that implement Power Management capability as defined by the PCI Bus Power Management Interface Specification, Revision 1.1, MSI, MSI-X, and Vital Private Data (VPD) capabilities as defined by PCI Local Bus Specification, Revision 2.3, and PCI Express capability as defined by PCI Express Base Specification, Revision 1.0a.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Figure 23.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.2 PCI Express Link Characteristics The PCI Express* port supports x8, x4, x2, and x1 operation. Lane reversal and polarity inversion automatically occur in an attempt to successfully train the link. The PCI Express port is configured to ease adapter card implementations. The lane number and lane polarity should enable straight routing between the component and the PCI Express card edge connector.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.3 ATU Address Translation The ATU allows PCI Express requesters to initiate transactions to the 4138xx internal bus and allows the Intel XScale® processor to initiate transactions in the PCI Express domain. The ATU implements an address windowing scheme to determine which addresses to claim and translate to the destination bus. • The address windowing mechanism for inbound translation is described in Section 3.3.1.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 The ATU unit allows for recognition and generation of multiple PCI Express Transaction Layer Packets (TLP) types. Table 120 shows the commands supported for both inbound and outbound ATU transactions. The type of operation seen by the ATU on inbound transactions are determined by the PCI Express requester who initiates the transaction.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Table 120.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.3.1 Inbound Transactions 3.3.1.1 Inbound Address Translation Inbound transactions are received on the PCI Express receive port and forward to the 4138xx internal bus. This transactions include all requests for which the ATU is the completer as well as completions for which the ATU was the initiator. Inbound request transactions which target the ATU are translated and executed on the 4138xx internal bus.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) • • • • Section 3.17.16, “Inbound ATU Base Address Register 1 - IABAR1” on page 308 Section 3.17.31, “Inbound ATU Limit Register 1 - IALR1” on page 320 Section 3.17.32, “Inbound ATU Translate Value Register 1 - IATVR1” on page 321 Section 3.17.33, “Inbound ATU Upper Translate Value Register 1 - IAUTVR1” on page 321 The ATU uses the following registers in inbound address window 2 translation: • Section 3.17.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Once the transaction is claimed, the upper 32-bits of the address is discarded and the lower 32-bits of the address must be translated from a PCI address to a 36-bit internal bus address. The algorithm is: Equation 9. Inbound Translation 4138xx Internal Bus Address = ((PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]) | (ATU_Upper_Translate Value_Register[3:0] << 32).
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.3.1.2 Inbound Memory Write Transaction An inbound write transaction is initiated by a PCI Express requester and is targeted at either 4138xx local memory or a 4138xx memory-mapped register.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.3.1.3 Inbound Memory Read Transaction An inbound read transaction is initiated by a PCI Express requester and is targeted at either 4138xx local memory or a 4138xx memory-mapped register space. The read transaction is propagated through the inbound non posted queue (INPQ) and read data is returned through outbound completion data and header queues (OCPLHQ, OCPLDQ). In PCI Express, all read transactions are processed as split transactions.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.3.1.4 Inbound I/O Cycle Translation 3.3.1.5 Inbound Configuration Cycle Translation (ID Routed) Inbound address window 2 can be configured to accept I/O Read and I/O Write transactions by setting the Memory/IO space indicator bit to 1 in the “Inbound ATU Base Address Register 2 - IABAR2” on page 310. All I/O cycles are 32-bit transactions (DWORD).
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.3.1.6 Inbound Vendor_Defined Message Transactions Inbound messages are routed to the PCI Express message unit where they are decoded and processed. Inbound Vendor_Defined Messages (IVM) are logged in the Inbound Message Header0-3 and Inbound®Message Payload registers and an interrupt is conditionally sent to the Intel XScale processor. Only one message can be pending in the Inbound Vendor Message registers at one time.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.3.2 Note: Outbound Transactions Outbound transactions initiated by the 4138xx core processor are directed to the PCI Express interface through the ATU. As a PCI Express requester, the ATU is capable of memory, I/O, configuration, and message transactions. Outbound memory transactions with addresses below 4GB use the short address format (32-bit address). Addresses above 4GB use the long address format (64-bit).
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.3.2.1 Outbound Address Translation - Internal Bus Transactions In addition to providing the mechanism for inbound translation, the ATU translates Intel XScale® processor-initiated cycles to the PCI Express domain. This is known as outbound address translation. Outbound transactions are processor or DMA transactions targeted at the PCI Express Link.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.3.2.2 Outbound Address Translation Windows Inbound translation involves a programmable inbound translation window consisting of a base and limit register and a value register for PCI to internal bus translation. The outbound address translation windows use a similar methodology except that the outbound translation window limit sizes are fixed in 4138xx internal bus address space; this removes the need for separate limit registers.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Figure 26.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) The translation portion of outbound ATU transactions is accomplished with a value register in the same manner as inbound translations. Each outbound memory window is associated with one translation register which provides the upper translation addresses (OUMWVR0-3). When the corresponding OUMWVRx register is all-zero a 3DW header transaction is generated on the PCI Express Link.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Figure 27.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.3.2.3 Outbound DMA Transactions 3.3.2.4 Outbound Function Number The ATU provides all ADMA channels with a transparent path through the PCI Express interface. The entire 64-bit Host I/O Interface address programmed in the DMA descriptor is passed to the PCI Express link unmodified.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.3.3 Outbound Write Transaction An outbound write transaction is initiated by the Intel XScale® processor9 or by one of the DMAs and is targeted at a PCI Express domain. The outbound write address and write data are propagated from the 4138xx internal bus to a PCI Express Link through the OPHQ and OPDQ, respectively. The ATUs internal bus target interface claims the write transaction and forwards it to the PCI Express Link.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.3.4 Outbound Read Transaction An outbound read transaction is initiated by the Intel XScale® processor10 or one of the DMAs and is targeted at a PCI slave on the PCI Express Link. The read transaction is propagated through the outbound non posted queue (ONPQ) and read data is returned through the inbound completion data queue (ICPLDQ).
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.3.5 Note: 3.3.5.1 3.3.5.2 Outbound Configuration Cycle Translation The outbound ATU provides a port programming model for outbound configuration cycles. Performing an outbound configuration cycle to the PCI Express Link involves up to two internal bus cycles: 1. Writing Outbound Configuration Cycle Address Register (OCCAR) with the bus, device, function, and register number used during the configuration cycle.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.3.5.3 Note: 3.3.5.4 Outbound PCI Express Message Transactions The ATU provides a port programming model to generate outbound PCI Express messages. Generating an outbound message transaction to the PCI Express interface involves up to 5 internal bus cycles. 1. Write outbound message transaction header registers 0 - 3. 2. Write the data to the outbound message transaction payload register.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.4 Note: 3.4.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.4.2 Note: Outbound Byte Swapping When enabled, the swapping occurs as described in Figure 29, “Outbound Byte Swapping for Transaction with Byte Count of 1” on page 256, Figure 30, “Outbound Byte Swapping for Transactions with Byte Count of 2” on page 256, and Figure 31, “Outbound Byte Swapping Transaction with Byte Count of 3 or Larger” on page 256.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.5 Messaging Unit The Messaging Unit (MU) is used to transfer data between the PCI system and the 4138xx and notifies the respective system when new data arrives. The MU is located on the south internal bus of the 4138xx and is accessed via the ATU. The MU is described in Chapter 4.0, “Messaging Unit”.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.6 PCI Express Messages PCI Express defines a new message mechanism that is used to communicate outside of the normal Memory, I/O, and Configuration Spaces. The messages received and initiated by 4138xx vary depending on whether the device is acting as a root complex or an endpoint. All the messages defined in the PCI Express specification and 4138xx’s actions are listed in Table 125. Table 125.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Table 125.
PAGE 260
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.7 Note: Expansion ROM Translation Unit The inbound ATU supports one address range (defined by a base/limit register pair) used for the Expansion ROM. Refer to the PCI Local Bus Specification, Revision 2.3 for details on Expansion ROM format and usage. During a powerup sequence, initialization code from Expansion ROM is executed once by the host processor to initialize the associated device. The code can be discarded once executed.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.8 ATU Queue Architecture 3.8.1 Inbound Queues ATU operation and performance depends on queueing mechanism implemented between internal bus interface and PCI Express interface. Figure 23 indicates the ATU queue architecture consists of separate inbound and outbound queues. The function of each queue is described in the following sections.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.8.1.2 Inbound Non Posted Queue Structure 3.8.1.3 Inbound Completion Queue Structure 3.8.1.4 Inbound Transaction Queues Command Translation Summary The inbound read queues are responsible for retrieving data from local memory and returning it to the PCI Express Link in response to a read transaction initiated from a PCI master. Up to 8 non posted transactions can be held in the INPQ.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.8.2 Outbound Queues The outbound queues of the ATU are used to hold read and write transactions from the core processor directed at the PCI Express Link. Each ATU outbound queue structure has a separate read queue, write queue, and address queue. Table 128 contains information about ATU outbound queues. Table 128.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.8.3 Note: Transaction Ordering Because the ATU can process multiple transactions, they must maintain proper ordering to avoid deadlock conditions and improve throughput. The ATU transaction ordering rules used by the 4138xx are listed in Table 129 for the inbound direction and Table 130 on page 265 for the outbound direction. The tables are based on the direction the transaction is moving, i.e.
PAGE 265
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Definitions of the terms used in Table 129 and Table 130 are as follows. PCI terms are noted in parenthesis: Table 130.
PAGE 266
Intel® 413808 and 413812—Address Translation Unit (PCI Express) In Example 2 on page 265, the inbound write and outbound read queues of the ATU are shown. In this example, transaction A entered the write queue at Time 0. Next, the ATU entered read data into the outbound read queue at Time 1 (Transaction B). Finally, before the previous transactions could be cleared, another inbound write, Transaction C, was entered into the IWQ.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.8.3.1 Transaction Ordering Summary Table 131 and Table 132, define transaction ordering in relation to token assignment of the priority mechanism (see Section 3.8.3). These tables are read as follows: 1. As transaction enters the respective queue head, the question in column 2 is asked. 2. When all the answers in column 3 for a given transaction type assigns a token to the transaction at the head of the queue, a token is assigned.
PAGE 268
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.8.4 Byte Parity Checking and Generation 3.8.4.1 Parity Generation The ATU internal bus interface supports byte-wise parity protection on the internal bus. This includes ADDP[4:0] and DATAP[15:0] on the address bus (A[35:0]) and the data bus (D[127:0]) respectively. For an outbound request the ATU check the address parity before claiming the request on the internal bus. When an error occurs, the transaction is not claimed.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.8.4.2 Parity Checking On an outbound request, address parity is checked on the address bus A[35:0]. The parity bits are checked by first bit XORing the address bits shown in Table 133 with the corresponding address parity bits, and then verifying when the result of each of the XORed operations are equal to zero. As an example, the parity calculation for the lowest order byte of the address bus A[7:0] is carried as follows: Equation 13.
PAGE 270
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.9 ATU Error Conditions PCI Express and internal bus error conditions cause ATU to log header information and set status bits to inform error handling code of exact cause of error condition. Two sets of registers are provided®to allow independent control by both the Host processor and the internal Intel XScale microarchitecture. Error conditions and status can be found in the ATUSR.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.9.1 PCI Express Errors 3.9.1.1 Role Based Error Reporting Note: PCI Express classifies errors as either Fatal, Uncorrectable or Correctable which allows the platform to map errors to a suitable handling mechanism. The control and mapping of errors into each of these categories are provided by the Advanced Error Handling registers.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.9.1.2 Malformed Packets 3.9.1.3 ECRC Check Failed The following checks are made to detect malformed TLPs. • Data Payload exceeds the length specified by the value in the Max_Payload_Size field of the Device Control Register. • The value in the length field and the actual amount of data received do not match. The value in the length field applies only to data, TLP digest is not included in the length.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.9.1.4 Note: 3.9.1.5 Note: 3.9.1.6 Note: Unsupported Request Unsupported Requests are detected by the address decode and translation logic. A TLP is treated as unsupported in the following cases: • the TLP fails to match any of the active Memory or I/O windows.
PAGE 274
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.9.1.7 Note: 3.9.1.8 Note: Poisoned TLP Received Poisoned TLPs can be received for both Inbound Posted (Write/Message) and Inbound Completions The two TLP types can be handled differently. Poisoned completions are passed through to the internal bus with bad parity.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.9.2 Parity Error on the Internal Bus 3.9.3 ATU Error Summary The 4138xx provides support for byte-wise parity protection on the internal bus. The internal bus consists of a 36 bit address bus and 128 bit data bus; both are protected by byte-wise parity. The internal bus parity protection is provided independent of the operating mode of the ATU’s PCI interface.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Table 135.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Table 135. PCI Express Error Summary (Sheet 2 of 2) Bus Protocol Actiona Error Condition Malformed TLP Receiver: Send ERR_FATAL/ ERR_NONFATAL to Root Complex Log the header of the TLP that caused the error.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Table 136.
PAGE 279
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.10 PCI Express Hot-Plug Support The PCI Express architecture is designed to natively support both Hot-Plug and hot remove of devices. This section defines the usage model defined for all the ATU. ATU supports the receipt and generation of Hot-Plug messages via the Inbound/Outbound message header registers.
PAGE 280
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.11 Reset The PCI Express specification defines three distinct types of reset: cold, warm, and hot. The fundamental reset that occurs following initial power on is considered a hot reset. The assertion of the PRST# or WARM_RST# pins are considered warm resets. The receipt of the inband reset training sequence is considered a hot reset. Sticky bits are preserved under the WARM_RST# and inband hot reset conditions.
PAGE 281
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.12 Message-Signaled Interrupts The Messaging Unit is responsible for the generation of all of the Outbound Interrupts from the 4138xx. These interrupts can be delivered to the Host Processor via the legacy Assert_INTx/Deassert_INTx messages or the Message Signaled Interrupt (MSI) mechanism.
PAGE 282
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.13 3.13.1 Vital Product Data Vital Product Data (VPD) provides detailed information to the system regarding the hardware, software and microcode elements of a device. This information may include Part Number, Serial Number or other detailed information. This information resides on a non-volatile storage device (i.e., Flash Memory) attached to the 4138xx.
PAGE 283
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.13.2 Accessing Vital Product Data 3.13.2.1 Reading Vital Product Data Warning: The VPD Capabilities List Item provides three fields which the system uses to access the Vital Product Data: VPD Address DWORD Aligned Byte address of the VPD to be accessed which is represented by VPDAR[14:0]. Note that this means that the maximum size of the VPD is 128 Kbytes.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.13.2.2 Warning: Writing Vital Product Data Using the fields defined in the VPD Capabilities List Item, the 4138xx writes Vital Product Data using the following sequence of events: 1. Host processor executes a configuration write of the VPD data to be written to the VPDDR. 2. Host processor executes a configuration write of the VPD address to the VPDAR with the Flag set. 3.
PAGE 285
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.14 Multi-Function Support 3.14.1 PCI Express Interface Control Parameters The 4138xx supports only one function, either ATU (TPER mode) or TPMI (IOC mode). The following registers are located in the configuration space header and extended space and provide control of the PCI Express Interface. The effect of each bit is detailed below. Table 138.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Table 138. PCI Express Interface Control Parameters Usage (Sheet 2 of 2)a Register Name Register Bits Description Usage PCI Express Uncorrectable Error Entire Register Each function can independently control these bits. Mask - ERRUNC_MSK PCI Express Uncorrectable Error Entire Register Each function can independently control these bit.
PAGE 287
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.14.2 PCI Express Interface Status Reporting The following registers are located in the configuration space header and extended space and provide status (error conditions) of the PCI Express Interface. Table 139. PCI Express Interface Status Reporting Usage a Register Name ATU Status Register - ATUSR Register Bits Description Usage TLP received is reported in Bit 15 - Detected Parity Error Poisoned the function involved.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.15 Root Complex Functionality 3.16 Embedded Bridge Functionality Note: Not supported on 4138xx. The 4138xx does not support Root Complex.
PAGE 289
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17 Register Definitions Every PCI device implements its own separate configuration address space and configuration registers. The PCI Express Specification extends the configuration space to 4096 bytes as compared to 256 bytes allowed by PCI Local Bus Specification, Revision 2.3. The ATU configuration space is divided into a PCI 2.
PAGE 290
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.1 Extended Capabilities Registers The ATU unit includes 5 extended capability configuration spaces beginning at configuration offset 90H, 98H, A0H, B0H, and D0H. The extended configuration spaces can be accessed by a device on the PCI interface through a mechanism defined in the PCI Express Specification. In the ATU Status Register (Section 3.17.
PAGE 291
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Figure 35. ATU Interface Extended Configuration Header Format (MSI Capability) MSI Next Item Pointer MSI Message Control MSI Capability ID A0H MSI Message Address A4H MSI Message Upper Address A8H Reserved MSI Message Data ACH The first byte at the Extended Configuration Offset D0H is the Section 4.7.20, “MSI Capability Identifier Register - Cap_ID” on page 429.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Note: The first byte at the Extended Configuration Offset 90H is the VPD Capability Identifier Register (Section 3.17.44). This identifies this Extended Configuration Header space as the type defined by the PCI Local Bus Specification, Revision 2.3. Following the Capability Identifier Register is the single byte Next Item Pointer Register (Section 3.17.
PAGE 293
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.2 Note: Internal Bus Addresses All of the ATU registers are accessible through both inbound PCI configuration cycles and the 4138xx core CPU (Register offsets 000H through 0FFH). T. The location of these registers are specified as a relative offset to a 512KB aligned global PMMR offset. The default for the 512KB aligned offset is 0 FFD8 0000H defined by the PMMRBAR register. See also Chapter 19.0, “Peripheral Registers”.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Table 141. ATU PCI Configuration Register Space (Sheet 1 of 3) Interna l Bus Address Offset +000H +002H +004H +006H +008H +009H +00CH +00DH +00EH +00FH +010H +014H +018H +01CH +020H +024H +02CH +02EH +030H +034H +03CH +03DH +03EH +03FH +040H +044H +048H +04CH +050H +054H +058H +05CH +060H +064H +068H +06CH +070H +074H +078H +07CH +080H +084H +090H +091H +092H ATU PCI Configuration Register Section, Name, Page Section 3.17.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Table 141. ATU PCI Configuration Register Space (Sheet 2 of 3) Interna l Bus Address Offset +094H +098H +099H +09AH +09CH +0A0H +0A1H +0A2H +0A4H +0A8H +0ACH +0B0H +0B1H +0B2H +0B4H +0B8H +0BCJ+0C8H +0CCH +0D0H +0D1H +0D2H +0D4H +0D8H +0DAH +0DCH +0E0H +0E2H +0E4H +0E8H +0EAH +0ECH +0F0H +100H +104H +108H +10CH +110H +114H +118H +11CH +120H +124H +128H +12CH +130H ATU PCI Configuration Register Section, Name, Page Section 3.17.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Table 141. ATU PCI Configuration Register Space (Sheet 3 of 3) Interna l Bus Address Offset ATU PCI Configuration Register Section, Name, Page +134H Section 3.17.82, “Error Source Identification Register - RERR_ID” on page 364 +1E0H Section 3.17.83, “Device Serial Number Capability - DSN_CAP” on page 364 +1E4H Section 3.17.84, “Device Serial Number Lower DW Register - DSN_LDW” on page 365 +1E8H Section 3.17.
PAGE 297
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.3 ATU Vendor ID Register - ATUVID ATU Vendor ID Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. Table 142. ATU Vendor ID Register - ATUVID 15 12 8 4 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw PCI Attributes ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro Attribute Legend: RV = Reserved PR = Preserved RS = Read/Set Internal Bus Address Offset +000H Bit Default 15:00 8086H 3.17.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.5 ATU Command Register - ATUCMD ATU Command Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3 and in most cases, affect the behavior of the PCI ATU and devices on the PCI Express Link. Table 144.
PAGE 299
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.6 ATU Status Register - ATUSR The ATU Status Register bits adhere to the PCI Local Bus Specification, Revision 2.3 definitions. The read/clear bits can only be set by internal hardware and cleared by either a reset condition or by writing a 12 to the register. Table 145.
PAGE 300
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.7 ATU Revision ID Register - ATURID Revision ID Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. Table 146.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.9 ATU Cacheline Size Register - ATUCLSR Cacheline Size Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register is programmed with the system cacheline size in DWORDs (32-bit words). Cacheline Size is restricted to either 0, 8 or 16 DWORDs; the ATU interprets any other value as “0”. Table 148.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.11 ATU Header Type Register - ATUHTR Header Type Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register indicates the layout of ATU configuration space bytes 10H to 3FH. The MSB indicates whether or not the device is multi-function. Table 150.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.12 ATU BIST Register - ATUBISTR The ATU BIST Register controls the functions the Intel XScale® processor performs when BIST is initiated. This register is the interface between the host processor requesting BIST functions and the 4138xx replying with the results from the software implementation of the BIST functionality. Table 151.
PAGE 304
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.13 Inbound ATU Base Address Register 0 - IABAR0 The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) defines the block of memory addresses where the inbound translation window 0 begins. The inbound ATU decodes and forwards the bus request to the 4138xx internal bus with a translated address to map into 4138xx local memory.
PAGE 305
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.14 Inbound ATU Upper Base Address Register 0 - IAUBAR0 This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI Express Link for addresses > 4 GBytes (for DACs).
PAGE 306
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.15 Determining Block Sizes for Base Address Registers The required address size and type can be determined by writing ones to a base address register and reading from the registers. By scanning the returned value from the least-significant bit of the base address registers upwards, the programmer can determine the required address space size.
PAGE 307
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Table 155.
PAGE 308
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.16 Inbound ATU Base Address Register 1 - IABAR1 The Inbound ATU Base Address Register 1 (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) defines the block of memory addresses where the inbound translation window 1 begins. The inbound ATU decodes and forwards the bus request to the 4138xx internal bus with a translated address to map into 4138xx local memory.
PAGE 309
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.17 Inbound ATU Upper Base Address Register 1 - IAUBAR1 This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI Express Link for addresses > 4GBytes (for DACs).
PAGE 310
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.18 Inbound ATU Base Address Register 2 - IABAR2 The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) defines the block of memory space or I/O space addresses where the inbound translation window 2 begins. The inbound ATU decodes and forwards the bus request to the 4138xx internal bus with a translated address to map into 4138xx local memory.
PAGE 311
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.19 Inbound ATU Upper Base Address Register 2 - IAUBAR2 This register contains the upper base address when decoding PCI addresses for memory space (Memory Space Indicator in IABAR2 is clear) beyond 4 GBytes. Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI Express Link for addresses > 4 GBytes (for DACs).
PAGE 312
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.20 ATU Subsystem Vendor ID Register - ASVIR ATU Subsystem Vendor ID Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. Table 160.
PAGE 313
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.22 Expansion ROM Base Address Register - ERBAR The Expansion ROM Base Address Register defines the block of memory addresses used for containing the Expansion ROM. It permits the inclusion of multiple code images, allowing the device to be initialized. The code image supplied consists of either executable code or an interpreted code. Each code image must start on a 512 byte boundary and each must contain the PCI Expansion ROM header.
PAGE 314
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.23 ATU Capabilities Pointer Register - ATU_Cap_Ptr The Capabilities Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register provides an offset in this function’s PCI Configuration Space for the location of the first item in the first Capability list.
PAGE 315
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.24 ATU Interrupt Line Register - ATUILR ATU Interrupt Line Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register identifies the system interrupt controller's interrupt request lines which connect to the device's PCI interrupt request lines (as specified in the interrupt pin register).
PAGE 316
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.25 ATU Interrupt Pin Register - ATUIPR ATU Interrupt Pin Register bit definitions adhere to PCI Local Bus Specification, Revision 2.3. This register identifies the interrupt pin the ATU and Messaging Unit interface uses. Table 165.
PAGE 317
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.27 ATU Maximum Latency Register - ATUMLAT This register does not apply to PCI Express. Table 167.
PAGE 318
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.28 Inbound ATU Limit Register 0 - IALR0 Inbound address translation for memory window 0 occurs for requests originating in the PCI Express domain and targeting the 4138xx internal bus. The address translation block converts PCI addresses to internal bus addresses. The inbound translation base address for inbound window 0 is specified in Section 3.17.13. When determining block size requirements — as described in Section 3.17.
PAGE 319
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.29 Inbound ATU Translate Value Register 0 - IATVR0 The Inbound ATU Translate Value Register 0 (IATVR0) in conjunction with the “Inbound ATU Upper Translate Value Register 0 - IAUTVR0” on page 319 contain bits 35 to 12 of the internal bus address used to convert PCI Express Link addresses. The converted address is driven on the internal bus as a result of the inbound ATU address translation. Table 169.
PAGE 320
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.31 Inbound ATU Limit Register 1 - IALR1 Inbound address translation for memory window 1 occurs for transactions originated in the PCI Express domain and targeting the 4138xx internal bus. The address translation block converts PCI addresses to internal bus addresses. The inbound translation base address for inbound window 1 is specified in Section 3.17.16. When determining block size requirements — as described in Section 3.17.
PAGE 321
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.32 Inbound ATU Translate Value Register 1 - IATVR1 The Inbound ATU Translate Value Register 1 (IATVR1) in conjunction with the “Inbound ATU Upper Translate Value Register 1 - IAUTVR1” on page 321 contain bits 35 to 12 of the internal bus address used to convert PCI Express Link addresses. The converted address is driven on the internal bus as a result of the Inbound ATU address translation. Table 172.
PAGE 322
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.34 Inbound ATU Limit Register 2 - IALR2 Inbound address translation for inbound window 2 occurs for transactions originated in the PCI Express domain and targeting the 4138xx internal bus. The address translation block converts PCI addresses to internal bus addresses. The inbound translation base address for inbound window 2 is specified in Section 3.17.18. When determining block size requirements — as described in Section 3.17.
PAGE 323
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.35 Inbound ATU Translate Value Register 2 - IATVR2 The Inbound ATU Translate Value Register 2 (IATVR2) in conjunction with the “Inbound ATU Upper Translate Value Register 2 - IAUTVR2” on page 324 contain bits 35 to 8 of the internal bus address used to convert PCI Express Link addresses. The converted address is driven on the internal bus as a result of the Inbound ATU address translation.
PAGE 324
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.36 Inbound ATU Upper Translate Value Register 2 - IAUTVR2 The Inbound ATU Upper Translate Value Register 2 (IAUTVR2) in conjunction with the “Inbound ATU Translate Value Register 2 - IATVR2” on page 323 contain bits 35 to 8 of the internal bus address used to convert PCI Express Link addresses. The converted address is driven on the internal bus as a result of the inbound ATU address translation. Table 176.
PAGE 325
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.38 Expansion ROM Translate Value Register - ERTVR The Expansion ROM Translate Value Register 0 (ERTVR) in conjunction with the “Expansion ROM Upper Translate Value Register - ERUTVR” on page 325 contain bits 35 to 12 of the internal bus address used to convert PCI Express Link addresses. The converted address is driven on the internal bus as a result of the Expansion ROM address translation. Table 178.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.40 ATU Configuration Register - ATUCR The ATU Configuration Register contains some additional parameters in the ATU. Table 180.
PAGE 327
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.41 PCI Configuration and Status Register - PCSR The PCI Configuration and Status Register has additional bits for controlling and monitoring various features of the PCI Express interface. The PCI Express Bus Number and Device Number are used to form the Requestor/Completer ID and should only be changed when operating as a Root Complex. These fields are updated whenever a type 0 configuration write targets the IOP.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Table 181.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.42 ATU Interrupt Status Register - ATUISR The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit of the 4138xx. All bits in this register are Read/Clear.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) Table 182.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Table 182.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.43 ATU Interrupt Mask Register - ATUIMR The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts generated by the ATU. Table 183.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.44 PCI Express Message Control/Status Register - PEMCSR The PCI Express Message Control/Status Register controls the generation and logs the receipt of PCI Express Power Management and Hot-Plug messages. Table 184.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.45 PCI Express Link Control/Status Register - PELCSR The PCI Express Link Control/Status Register controls various parameters of the Link Layer including Training Sequence. When operating as an endpoint, these bits operate as status bits and reflect the settings of the most recent TS1/TS2 training sequences. When operating as a Root Complex, these bits are control bits that are used when sending the training sequences.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.46 VPD Capability Identifier Register - VPD_Cap_ID The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended Capability contained in that header. In the case of the 4138xx, this is the VPD extended capability with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. Table 186.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.48 VPD Address Register - VPDAR The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be accessed. The register is read/write and the initial value at power-up is indeterminate. A PCI Configuration Write to the VPDAR interrupts the Intel XScale® processor.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.50 PM Capability Identifier Register - PM_Cap_ID The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended Capability contained in that header.
PAGE 338
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.52 ATU Power Management Capabilities Register - APMCR Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides information on the capabilities of the ATU function related to power management. Table 192.
PAGE 339
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.53 ATU Power Management Control/Status Register - APMCSR Note: Power Management Control/Status bits adhere to the definitions in the PCI Bus Power Management Interface Specification, Revision 1.1. This 16-bit register is the control and status interface for the power management extended capability. Some bits in this register are sticky through reset. Table 193.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.54 ATU Scratch Pad Register - ATUSPR This register can be used for application specific purposes and has no direct impact on the hardware. Table 194.
PAGE 341
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.56 PCI Express Next Item Pointer Register - PCIE_NXTP Warning: The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register describes the location of the next item in the function’s capability list. By default, the PCI Express capability is the last capabilities list for the 4138xx, thus this register defaults to 00H.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.57 PCI Express Capabilities Register - PCIE_CAP This register controls various modes and features of ATU and Message Unit when operating in the PCI Express mode. Table 197.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.58 PCI Express Device Capabilities Register - PCIE_DCAP This register identifies the capabilities and current operating mode of ATU, DMAs and Message Unit when operating in the PCI Express mode. Table 198.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.59 PCI Express Device Control Register - PE_DCTL This register controls various modes and features of ATU and Message Unit when operating in the PCI Express mode. Table 199.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 Table 199.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.60 PCI Express Device Status Register - PE_DSTS This register controls various modes and features of ATU and Message Unit when operating in the PCI Express mode. Table 200.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.61 PCI Express Link Capabilities Register - PE_LCAP This register identifies the capabilities and current operating mode of ATU, DMAs and Message Unit when operating in the PCI Express mode. Table 201.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.62 PCI Express Link Control Register - PE_LCTL This register controls various modes and features of ATU and Message Unit when operating in the PCI Express mode. Table 202.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.63 PCI Express Link Status Register - PE_LSTS This register controls various modes and features of ATU and Message Unit when operating in the PCI Express mode. Table 203.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.64 PCI Express Slot Capabilities Register - PE_SCAP This register identifies PCI Express slot specific capabilities. Table 204.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.65 PCI Express Slot Control Register - PE_SCR This register controls PCI Express Slot specific parameters. 4138xx does not implement Hot-Plug support for its downstream ports when operating as a root complex. This is left as R/W for the IOP in case a software solution can be implemented using the GPIO pins. Table 205.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.66 PCI Express Slot Status Register - PE_SSTS This register provides information about PCI Express Slot specific parameters. 4138xx does not implement Hot-Plug support for its downstream ports when operating as a root complex. This is left as R/W for the IOP in case a software solution can be implemented using the GPIO pins. Table 206. PCI Express Slot Status Register PE_SSTS .
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.67 PCI Express Root Control Register - PE_RCR This register controls PCI Express Slot specific parameters. Table 207.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.68 PCI Express Root Status Register - PE_RSR The Root Statue Register provides information about PCI Express device specific parameters. Table 208.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.70 PCI Express Uncorrectable Error Status - ERRUNC_STS The Uncorrectable Error Status register indicates error detection status of individual uncorrectable errors on a PCI Express device. An individual error status bit that is set to “1” indicates that a particular error was detected; software may clear an error status by writing a 1 to the respective bit. All bits in this register are sticky through reset. Note: Table 210.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.71 PCI Express Uncorrectable Error Mask - ERRUNC_MSK The Uncorrectable Error Mask register controls reporting of individual errors by the device to the PCI Express Root Complex via a PCI Express error message. A masked error (respective bit set to 1b in the mask register) is not logged in the Header Log register, does not update the First Error Pointer, and is not reported to the PCI Express Root Complex by an individual device.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.72 PCI Express Uncorrectable Error Severity - ERRUNC_SEV The Uncorrectable Error Severity register controls whether an individual uncorrectable error is reported as a non-fatal or fatal error. An error is reported as fatal when the corresponding error bit in the severity register is set. When the bit is cleared, the corresponding error is considered non-fatal. All bits in this register are sticky through reset. Note: Table 212.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.73 PCI Express Correctable Error Status - ERRCOR_STS The Correctable Error Status register reports error status of individual correctable error sources on a PCI Express device. When an individual error status bit is set to “1” it indicates that a particular error occurred; software may clear an error status by writing a 1 to the respective bit All bits in this register are sticky through reset. Note: Table 213.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.74 PCI Express Correctable Error Mask - ERRCOR_MSK The Correctable Error Mask register controls reporting of individual correctable errors via ERR_COR message. A masked error (respective bit set in mask register) is not reported to the PCI Express Root Complex. There is a mask bit per error bit in the Correctable Error Status register. All bits in this register are sticky through reset. Note: Table 214.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.75 Advanced Error Control and Capability Register - ADVERR_CTL The register gives the status and control for ECRC checks and also the pointer to the first uncorrectable error that happened. All bits in this register are sticky through reset. Note: Table 215.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.77 PCI Express Advanced Error Header Log - ADVERR_LOG1 Transaction header log for PCI Express error. Table 217.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.79 PCI Express Advanced Error Header Log - ADVERR_LOG3 Transaction header log for PCI Express error. Table 219.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.81 Root Error Status Register When operating as the root complex of the PCI Express domain, the Root Error Status Register reports the status of error messages received by the ATU, and of errors detected by the ATU. Each correctable and uncorrectable (FATAL/NONFATAL) error source has a first error bit and a next error bit.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.82 Error Source Identification Register - RERR_ID The Root Error Command Register is used to notify the Intel XScale® processor in response to PCI Express Error Messages. This bits enable or disable the generation of the ATU Root Complex error interrupt. All bits in this register are sticky through reset. Note: Table 222.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.84 Device Serial Number Lower DW Register - DSN_LDW The Serial Number register is a 64-bit field that contains the IEEE defined 64-bit extended unique identifier (EUI-64TM). This identifier includes a 24-bit company id value assigned by IEEE registration authority and a 40-bit extension identifier assigned by the manufacturer. Table 224.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.86 PCI Express Advisory Error Control Register - PIE_AEC This registers enables Advisory Error functionality for devices that attempts to recover from certain errors. Firmware can attempt to recover from these non-fatal conditions zero, once, or more (finite) times. Once the retry limit has been reached the generate ERR_NONFATAL bit should be set to alert the host to problem. Table 226.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.87 Power Budgeting Enhanced Capability Header - PWRBGT_CAPID This register defines the power budgeting capability identifier. Table 227.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.89 Power Budgeting Data Register - PWRBGT_DATA This read-only register returns the DWORD of Power Budgeting Data selected by the Data Select Register. The values of one of the Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23] is returned when this register is read. Table 229.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.90 Power Budgeting Capability Register - PWRBGT_CAP Table 230.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.91 Power Budgeting Information Registers[0:23]—PWRBGT_INFO[0:23] There are 24 power budgeting information registers that are used to report power consumption information for power states as defined in the PCI Express Base Specification, Revision 1.0a. These registers are reflected in the Power Budgeting Data Register - PWRBGT_DATA based on the setting of the Data Select field in the Power Budgeting Data Select Register - PWRBGT_DSEL.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.92 Outbound I/O Base Address Register - OIOBAR The OIOBAR register locates the 64 KB I/O cycle address window in the 4138xx’s 64 Gbyte internal address space. When A[35:16] of the internal bus address matches the value in OIOBAR, the ATU claims the transaction and forward it over to the PCI interface as an I/O cycle.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.93 Outbound I/O Window Translate Value Register - OIOWTVR The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address used to convert the internal bus access to a PCI address. This address is driven on the PCI Express Link as a result of the outbound ATU address translation. See Section 3.3.2.1, “Outbound Address Translation - Internal Bus Transactions” on page 245 for details on outbound address translation.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.94 Outbound Upper Memory Window Base Address Register 0 OUMBAR0 The OUMBAR0 register locates Outbound Memory Window 0 in a 4 Gbyte Memory section in the 4138xx’s 64 Gbyte internal address space. When A[35:32] of the internal bus address matches the value in OUMBAR[3:0], the ATU claims the transaction and forward it over to the PCI Express interface.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.95 Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to directly address anywhere within the 64-bit host address space. When this register is all-zero, then a 3DW header is generated on the PCI Express Link. Table 235.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.96 Outbound Upper Memory Window Base Address Register 1 OUMBAR1 The OUMBAR1 register locates Outbound Memory Window 1 in a 4 Gbyte Memory section in the 4138xx’s 64 Gbyte internal address space. When internal bus address A[35:32] matches the value in OUMBAR1, the ATU claims the transaction and forward it over to the PCI interface.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.97 Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to directly address anywhere within the 64-bit host address space. When this register is all-zero, then a 3DW header is generated on the PCI Express Link. Table 237.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.98 Outbound Upper Memory Window Base Address Register 2 OUMBAR2 The OUMBAR2 register locates Outbound Memory Window 2 in a 4 Gbyte Memory section in the 4138xx’s 64 Gbyte internal address space. When A[35:32] of the internal bus address matches the value in OUMBAR2[3:0], the ATU claims the transaction and forward it over to the PCI interface.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.99 Outbound Upper 32-bit Memory Window Translate Value Register 2 - OUMWTVR2 The Outbound Upper 32-bit Memory Window Translate Value Register 2 (OUMWTVR2) defines the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to directly address anywhere within the 64-bit host address space. When this register is all-zero, then a 3DW header is generated on the PCI bus. Table 239.
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Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.100 Outbound Upper Memory Window Base Address Register 3 OUMBAR3 The OUMBAR3 register locates Outbound Memory Window 3 in a 4 Gbyte Memory section in the 4138xx’s 64 Gbyte internal address space. When A[35:32] of the internal bus address matches the value in OUMBAR3[3:0], the ATU claims the transaction and forward it over to the PCI interface.
PAGE 380
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.101 Outbound Upper 32-bit Memory Window Translate Value Register 3 - OUMWTVR3 The Outbound Upper 32-bit Memory Window Translate Value Register 3 (OUMWTVR3) defines the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to directly address anywhere within the 64-bit host address space. When this register is all-zero, then a 3DW header is generated on the PCI bus. Table 241.
PAGE 381
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.102 Outbound Configuration Cycle Address Register - OCCAR The Outbound Configuration Cycle Address Register is used to hold bytes 8-11 of the configuration transaction header. The Intel XScale® processor writes the bus, device, function, and register number which then enables the outbound configuration read or write.
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Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.103 Outbound Configuration Cycle Data Register - OCCDR The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write transaction on the PCI Express Link. The register is logical rather than physical meaning that it is an address not a register.
PAGE 383
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.104 Outbound Configuration Cycle Function Number - OCCFN This registers contains the function number that is used as part of the Requester ID for all outbound configuration requests. This field is also used to determine where errors get logged. For 4138xx the function number should be 0 for endpoint usage and 5 for Root Complex modes. Note: Table 244.
PAGE 384
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.105 Inbound Vendor Message Header Register 0 - IVMHR0 The Inbound Vendor Message Header Registers capture the header for a vendor defined message received on the PCI Express interface. Once the inbound message has been processed, the Inbound Vendor Message Received bit is set in the ATU Interrupt Status Register - ATUISR.
PAGE 385
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.106 Inbound Vendor Message Header Register 1 - IVMHR1 The Inbound Vendor Message Header Registers capture the header for a vendor defined message received on the PCI Express interface. Once the inbound message has been processed, the Inbound Vendor Message Received bit is set in the ATU Interrupt Status Register - ATUISR.
PAGE 386
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.107 Inbound Vendor Message Header Register 2 - IVMHR2 The Inbound Vendor Message Header Registers capture the header for a vendor defined message received on the PCI Express interface. Once the inbound message has been processed, the Inbound Vendor Message Received bit is set in the ATU Interrupt Status Register - ATUISR.
PAGE 387
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.108 Inbound Vendor Message Header Register 3 - IVMHR3 Inbound Vendor Message Header Registers capture the header for a vendor defined message received on the PCI Express interface. Once the inbound message is processed, the Inbound Vendor Message Received bit is set in the ATU Interrupt Status Register - ATUISR.
PAGE 388
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.110 Outbound Vendor Message Header Register 0 - OVMHR0 The Outbound Vendor Message Header Registers allow software to create a header that is used for a Vendor_Defined Message TLP. The OVMHR0-3 registers must be programmed prior to writing the Outbound Vendor Defined Message Payload Register OVMPR. A write to the OVMPR initiates the Vendor_Defined Message TLP.
PAGE 389
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.111 Outbound Vendor Message Header Register 1 - OVMHR1 The Outbound Vendor Message Header Registers allow software to create a header that is used for a Vendor_Defined Message TLP. The OVMHR0-3 registers must be programmed prior to writing the Outbound Vendor Defined Message Payload Register OVMPR. A write to the OVMPR initiates the Vendor_Defined Message TLP.
PAGE 390
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.112 Outbound Vendor Message Header Register 2 - OVMHR2 The Outbound Vendor Message Header Registers allow software to create a header that is used for a Vendor_Defined Message TLP. The OVMHR0-3 registers must be programmed prior to writing the Outbound Vendor Defined Message Payload Register OVMPR. A write to the OVMPR initiates the Vendor_Defined Message TLP.
PAGE 391
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.114 Outbound Vendor Message Payload Register - OVMPR The Outbound Vendor Message Payload Register contains the payload data that is used for the Vendor_Defined Message TLP. A write to this register initiates the Vendor_Defined Message on the PCI Express Interface. When a zero length payload is desired, then a write to this register is required to initiate the transaction, but the value written is ignored.
PAGE 392
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.115 PCI Interface Error Control and Status Register - PIE_CSR This register indicates whether or not the ATU has detected and logged a PCI interface error. The register is also used to enabled the logging of additional errors. For more details, see Section 3.9, “ATU Error Conditions” on page 270. Table 255.
PAGE 393
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.116 PCI Interface Error Status - PIE_STS The PCI Interface Error Status register reports error status of individual uncorrectable error sources. An individual error status bit that is set to “1” indicates that a particular error occurred; software may clear an error status by writing a 1 to the respective bit. The status bits are set even when the reporting of the error is masked in the PIE_MSK register. Note: Table 256.
PAGE 394
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.117 PCI Interface Error Mask - PIE_MSK The PCI Interface Error Mask register controls reporting of individual errors by the device to the Intel XScale® processor core via an interrupt (ATUISR bit 10). A masked error (respective bit set to 1b in the mask register) is not logged in the Header Log register, does not update the First Error Pointer, and generate an interrupt to the core. Table 257.
PAGE 395
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.118 PCI Interface Error Header Log - PIE_LOG0 Transaction header log for PCI interface errors. Table 258.
PAGE 396
Intel® 413808 and 413812—Address Translation Unit (PCI Express) 3.17.120 PCI Interface Error Header Log 2 - PIE_LOG2 Transaction header log for PCI interface errors. Table 260.
PAGE 397
Address Translation Unit (PCI Express)—Intel® 413808 and 413812 3.17.122 PCI Interface Error Descriptor Log Descriptor log for transaction errors. Table 262.
PAGE 398
Intel® 413808 and 413812—Messaging Unit 4.0 Messaging Unit This chapter describes the Messaging Unit (MU) of the Intel® 413808 and 413812 I/O Controllers (4138xx). 4.1 Overview The Messaging Unit (MU) provides a mechanism for data to be transferred between the PCI bus and the Intel XScale® processor and notifying the respective system of the arrival of new data through an interrupt. The MU can be used to send and receive messages. The MU is located on the south internal bus of the 4138xx.
PAGE 399
Messaging Unit—Intel® 413808 and 413812 4.2 Theory of Operation The MU has two independent messaging mechanisms. The Message Registers are similar to a combination of mailbox and doorbell registers. Each holds a 32-bit value and generates an interrupt when written. The two Doorbell Registers support software interrupts. When a bit is set in a Doorbell Register, an interrupt is generated.
PAGE 400
Intel® 413808 and 413812—Messaging Unit Figure 39.
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Messaging Unit—Intel® 413808 and 413812 Figure 40.
PAGE 402
Intel® 413808 and 413812—Messaging Unit 4.2.1 Transaction Ordering From a PCI standpoint, the Messaging Unit is a piece of the ATU and therefore must maintain ordering requirements against ATU transactions. Transaction ordering is achieved for the Index Registers, the Doorbell Register, and the Message Registers since these transactions are routed through the standard set of ATU read/write queues.
PAGE 403
Messaging Unit—Intel® 413808 and 413812 4.3 Message Registers 4.3.1 Outbound Messages 4.3.2 Inbound Messages Messages can be sent and received by the 4138xx through the use of the Message Registers. When written, ®the message registers may cause an interrupt to be generated to either the Intel XScale processor or the host processor. Inbound messages are sent by the host processor and received by the 4138xx. Outbound messages are sent by the 4138xx and received by the host processor.
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Intel® 413808 and 413812—Messaging Unit 4.4 Doorbell Registers There are two Doorbell Registers: the Inbound Doorbell Register and the Outbound Doorbell Register. The Inbound Doorbell® Register allows external PCI agents to generate interrupts to the Intel XScale processor. The Outbound Doorbell Register allows the Intel XScale® processor to generate a PCI interrupt. Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4.4.1 Outbound Doorbells 4.4.
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Messaging Unit—Intel® 413808 and 413812 4.5 Messaging Unit Error Conditions The Messaging Unit, like the ATU, encounters error conditions on the host I/O interface as well as the internal bus interface. As a host I/O interface target, all host I/O interface errors are captured and recorded in the ATU Status Register and can be masked using the ATU mechanisms. Refer to Chapter 2.0, “Address Translation Unit (PCI-X)” or Chapter 3.0, “Address Translation Unit (PCI Express)” for further details.
PAGE 406
Intel® 413808 and 413812—Messaging Unit 4.6 4.6.1 Message-Signaled Interrupts MSI Capability Structure When a host processor enables Message-Signaled Interrupts (MSI) on the 4138xx ATU function, the ATU function (MU) is responsible to signal interrupt to the host via a host I/O interface write instead of the assertion of the P_INTA# output pin. The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.
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Messaging Unit—Intel® 413808 and 413812 4.6.2 Note: MSI-X Capability and Table Structures Similar to MSI Capability, when a host processor enables Message-Signaled Interrupts (MSI-X) on the 4138xx ATU function, the ATU function (MU) is responsible to signal interrupt to the host via a PCI write instead of the assertion of the P_INTA#output pin. The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.
PAGE 408
Intel® 413808 and 413812—Messaging Unit Note: Note: To signal an Outbound Interrupt with MSI-X enabled, the 4138xx creates an outbound write transaction using the Message Address and the Message Data of the associated entry. On 4138xx, entry 0 of the MSI-X Table is assigned to bit OISR[0], entry 1 is assigned to bit OISR[1] and so on. For example, entry 7 of the MSI-X Table is assigned to bit OISR[7]. Entry 2 is assigned to bits OSIR[2] and OISR[31].
PAGE 409
Messaging Unit—Intel® 413808 and 413812 Figure 42 shows how the MSI-X Table and Pending Bits Array are mapped from the host I/O interface. The MU registers are located in the first 4-KByte of the 8-KByte address space. Figure 42. MSI-X Table and PBA Address Mapping Layout relative to the Internal Bus Offset Relative to PMMRBAR + 4000H 4 KB MU Registers + 5000H + 5800H MSI-X Table 2 KB MSI-X PBA 2 KB 8 KBytes 4 KB B6217-01 4.6.
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Intel® 413808 and 413812—Messaging Unit 4.7 Register Definitions The following registers are located in the Host I/O Interface address space and in the Peripheral Memory-Mapped Register (PMMR) address space. They are®accessible through host I/O interface bus transactions and through Intel XScale processor internal bus accesses. In the Host I/O Interface address space, they are mapped into the first 80 bytes of the inbound address window of the ATU.
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Messaging Unit—Intel® 413808 and 413812 Table 265. Message Unit Registers Internal Bus Address Offset Section, Register Name - Acronym (Page) 4010H 4014H 4018H 401CH 4020H 4024H 4028H 402CH 4030H 4034H 4038H 403CH 4048H 4050H 4084H 4088H 408CH - 4FFCH 50X0H1 50X4H2 50X8H3 50XCH4 5080H - 57FCH 5800H 5804H - 5FFCH Section 4.7.1, “Inbound Message Register - IMRx” on page 412 Section 4.7.1, “Inbound Message Register - IMRx” on page 412 Section 4.7.2, “Outbound Message Register - OMRx” on page 412 Section 4.
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Intel® 413808 and 413812—Messaging Unit 4.7.1 Inbound Message Register - IMRx There are two Inbound Message Registers: IMR0 and IMR1. When the IMR register is written, an interrupt to the Intel XScale® processor may be generated. The interrupt is recorded in the Inbound Interrupt Status Register and may be masked by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. Table 266.
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Messaging Unit—Intel® 413808 and 413812 4.7.3 Inbound Doorbell Register - IDR The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale® processor. Bit 31 is reserved for generating an Error Doorbell® interrupt. When bit 31 is set, an Error interrupt may be generated to the Intel XScale processor.
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Intel® 413808 and 413812—Messaging Unit 4.7.4 Inbound Interrupt Status Register - IISR The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. It records the status of Intel XScale® processor interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues.
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Messaging Unit—Intel® 413808 and 413812 4.7.5 Inbound Interrupt Mask Register - IIMR The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale® processor interrupts generated by the Messaging Unit. Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. They only affect the generation of the Intel XScale® processor interrupt.
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Intel® 413808 and 413812—Messaging Unit 4.7.6 Outbound Doorbell Register - ODR The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel XScale® processor to generate Host I/O Interface interrupts to the host processor by writing to the Software Interrupt bits or to a specific Host I/O Interface interrupt bit.
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Messaging Unit—Intel® 413808 and 413812 4.7.7 Outbound Interrupt Status Register - OISR The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the status of Host I/O Interface interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. The generation of Host I/O Interface interrupts recorded in the Outbound Interrupt Status Register may be masked by setting the corresponding bit in the Outbound Interrupt Mask Register.
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Intel® 413808 and 413812—Messaging Unit 4.7.8 Outbound Interrupt Mask Register - OIMR The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound Host I/O Interface interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the Host I/O Interface interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated.
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Messaging Unit—Intel® 413808 and 413812 4.7.9 Inbound Reset Control and Status Register - IRCSR The Inbound Reset Control and Status Register (IRCSR) provides the ability for the Host processor to request a Selective Reset or a Coordinate Reset. A selective reset is used to perform a soft reset. A selective reset is requested by the host processor setting the Selective Reset bit of the IRCSR, which causes an Intel XScale® processor interrupt.
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Intel® 413808 and 413812—Messaging Unit 4.7.10 Outbound Reset Control and Status Register - ORCSR The Outbound Reset Control and Status Register (ORCSR) provides the ability for the I/O-processor to coordinate a hardware reset with the Host processor when multi-function is being used. In a multi-function scenario, before the Host driver can issue a hardware reset via one of the functions, all the host drivers running must be quiesced.
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Messaging Unit—Intel® 413808 and 413812 4.7.11 MSI Inbound Message Register — MIMR The MSI Inbound Message (MIMR) is a 16-bit data register that can be used to receive inbound MSI interrupt (Message-Signaled Interrupt) from external PCI devices. When operating as a Root Complex (ATU-E) or Central Resource (ATU-X) device, an external PCI device can signal an interrupt by writing the MSI Inbound Message Register.
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Intel® 413808 and 413812—Messaging Unit 4.7.12 MU Configuration Register - MUCR The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. The Circular Queue Enable bit enables or disables the Circular Queues. The Circular Queues are disabled at reset to allow the software to initialize the head and tail pointer registers before any PCI accesses to the Queue Ports.
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Messaging Unit—Intel® 413808 and 413812 4.7.13 MU Base Address Register - MUBAR MU Base Address Register (MUBAR) contains lower 32-bit of the 36-bit local memory base address of the MU address space as depicted in Figure 39. For example, the MU address space as viewed from Host I/O Interface. The MU base address is required to be located on an 8-KByte boundary. The upper four-bits of the MU Base Address are located in the MU Upper Address Register (MUBAR). Refer to Section 4.7.
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Intel® 413808 and 413812—Messaging Unit 4.7.14 MU Upper Base Address Register - MUUBAR The MU Upper Base Address Register (MUUBAR) contains the upper 4-bit of the 36-bit local memory base address of the MU address space as depicted in Figure 39. For example, the MU address space as viewed from Host I/O Interface interface. The MU base address is required to be located on a 8-KByte boundary. The lower 32-bits of the MU Base Address are located in the MU Upper Address Register (MUBAR). Refer to Section 4.
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Messaging Unit—Intel® 413808 and 413812 4.7.15 MU MSI-X Table Message Address Registers - M_MT_MAR[0:7] The MU MSI-X Table Message Address Register contains the lower 30 bits of the MSI-X message address. An entry in the MSI-X Table is made up of four DWORDs. The M_MT_MAR[0:7] registers are not reset with an internal bus reset. Note: Table 280.
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Intel® 413808 and 413812—Messaging Unit 4.7.16 MU MSI-X Table Message Upper Address Registers M_MT_MUAR[0:7] The MU MSI-X Table Message Upper Address Register contains the upper 32 bits of the MSI-X message address. An entry in the MSI-X Table is made up of four DWORDs. The M_MT_MUAR[0:7] registers are not reset with an internal bus reset. Note: Table 281.
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Messaging Unit—Intel® 413808 and 413812 4.7.17 MU MSI-X Table Message Data Registers - M_MT_MDR[0:7] The MU MSI-X Table Message Data Register contains the message data of the MSI-X message. An entry in the MSI-X Table is made up of four DWORDs. The M_MT_MDR[0:7] registers are not reset with an internal bus reset. Note: Table 282.
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Intel® 413808 and 413812—Messaging Unit 4.7.18 MU MSI-X Table Message Vector Control Registers M_MT_MVCR[0:7] The MU MSI-X Table Message Vector Control Register contains the mask bit for this entry in the MSI-X Table. An entry in the MSI-X Table is made up of four DWORDs. The M_MT_MVCR[0:7] registers are not reset with an internal bus reset. Note: Table 283.
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Messaging Unit—Intel® 413808 and 413812 4.7.19 MU MSI-X Pending Bits Array Register - M_MPBAR The MU MSI-X Pending Bits Array Register contains the contains the pending bits for the eight MU interrupt sources. When an entry in the MSI-X table is masked in the Vector Control Register, the software may service that interrupt request by polling the pending bit. The M_MPBAR register is not reset with an internal bus reset. Note: Table 284.
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Intel® 413808 and 413812—Messaging Unit 4.7.21 Note: MSI Next Item Pointer Register - MSI_Next_Ptr The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.2. This register describes the location of the next item in the function capability list. For the 4138xx that is the PCI-X capability header at offset E0H. Refer to the Peripheral Registers Chapter for the default internal bus address.
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Messaging Unit—Intel® 413808 and 413812 4.7.22 Note: Message Control Register - Message_Control The Message Control Register provides system software control over MSI. After reset, MSI is disabled. System software is permitted to modify the Message Control register’s read/write bits and fields while a device driver is not permitted to modify them. Refer to the Peripheral Registers Chapter for the default internal bus address.
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Intel® 413808 and 413812—Messaging Unit 4.7.23 Message Address Register - Message_Address The Message address register specifies the DWORD aligned address for the MSI memory write transaction. The value is set by system software during initialization. Refer to the Peripheral Registers Chapter for the default internal bus address. This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint. Note: Table 288.
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Messaging Unit—Intel® 413808 and 413812 4.7.24 Message Upper Address Register - Message_Upper_Address The Message Upper Address register is set during system initialization when system software wishes to place the MSI address location above the 4G address boundary. When this register is set to a non-zero value, the 4138xx generates a dual address cycle for the MSI write command and uses the contents of this register as the upper 32-bits of that address.
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Intel® 413808 and 413812—Messaging Unit 4.7.25 Note: Message Data Register- Message_Data The value in the Message Data Register contains the data used during an MSI write transaction. When two unique messages are enabled, one message is reserved for the Outbound Post Queue Interrupt and the other message represents all of the Outbound Doorbell and Outbound Message Interrupts. When only one message is enabled, all of these interrupts are represented by a single message.
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Messaging Unit—Intel® 413808 and 413812 4.7.26 Note: MSI-X Capability Identifier Register - MSI-X_Cap_ID The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended Capability contained in that header.
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Intel® 413808 and 413812—Messaging Unit 4.7.27 Note: MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register describes the location of the next item in the function’s capability list. For the 4138xx, the next capability (PCI-X capability list) is located at off-set E0H. Refer to the Peripheral Registers Chapter for the default internal bus address.
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Messaging Unit—Intel® 413808 and 413812 4.7.28 Note: MSI-X Message Control Register - MSI-X_MCR MSI-X Capabilities bits adhere to the definitions in the PCI Local Bus Specification, Revision 2.3. This register is a 16-bit read-only register which provides information on the capabilities of the ATU function related to Message Signaled Interrupts. Refer to the Peripheral Registers Chapter for the default internal bus address.
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Intel® 413808 and 413812—Messaging Unit 4.7.29 MSI-X Table Offset Register — MSI-X_Table_Offset This register indicates in which PCI Memory Window the MSI-X Table is mapped. This register also provides an offset in the specified PCI Memory Window of where the MSI-X Table begins. Refer to the Peripheral Registers Chapter for the default internal bus address. This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint. Note: Table 294.
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Messaging Unit—Intel® 413808 and 413812 4.7.30 MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset This register indicates in which PCI Memory Window the MSI-X PBA is mapped. This register also provides an offset in the specified PCI Memory Window of where the MSI-X PBA begins. Refer to the Peripheral Registers Chapter for the default internal bus address. This register is part of the configuration space of the Address Translation Unit that is setup as an endpoint. Note: Table 295.
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Intel® 413808 and 413812—Messaging Unit 4.7.31 MU MSI-X Control Register X — MMCRx By default, the MU can generate up to eight MSI-X messages. The MMCRx register provides a control bit that allows collapsing the eight MSI-X messages down to only a single message. When the Host processor cannot honor the eight requested MSI-X messages, the MU MSI-X Single Message Vector bit can be set to cause only a single MSI-X message to be generated. Table 296.
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Messaging Unit—Intel® 413808 and 413812 4.7.32 Inbound MSI Interrupt Pending Register x — IMIPRx The Inbound MSI Interrupt Pending register is a 32-bit register that is used to post the one-hot decoded bits that are generated by the MU (Messaging Unit) when receiving inbound MSI (Message-Signaled Interrupt). The MU can generate up to 128 interrupts. Refer to the MSI Inbound Message Register — MIMR in®the MU Chapter.
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Intel® 413808 and 413812—SRAM DMA Unit (SDMA) 5.0 SRAM DMA Unit (SDMA) 5.1 Introduction 5.2 Overview This chapter describes the operation and control of the SRAM DMA (SDMA) Unit. The SRAM DMA (SDMA) unit provides a means for memory to be transferred between local memory (SRAM) and host memory through the PCIe bus. The SDMA provides two separate channels (HostToLocal and LocalToHost) that operate independently from one another.
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SRAM DMA Unit (SDMA)—Intel® 413808 and 413812 5.3 Theory of Operation To perform a DMA operation, the firmware writes to either the HostToLocal or LocalToHost registers, depending on the direction of transfer. One DMA is underway in each direction simultaneously. Each SDMA channel provides a “single-shot” DMA capability, in other words, one DMA operation at a time. There is no ability to queue multiple DMA requests in a given channel.
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Intel® 413808 and 413812—SRAM DMA Unit (SDMA) Example 3. Pseudo Code Programming Example: (RedBoot* command line prompts shown) To perform a single shot DMA of 0x40 from local SRAM offset 0x0 to host address 0x20_0000: INITIAL SETUP: 1. Assure the registers are enabled for access by setting bit 0 of the control/status register. mfill -b 0xFFD9823c -l 0x4 -p 0x1 2. Unmask SDMA error and status registers in INTCTL2 bits 12 and 13. TO PERFORM A DMA: 1.
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SRAM DMA Unit (SDMA)—Intel® 413808 and 413812 5.3.1 Interrupt Control for SDMA Refer to the silicon C Spec for full register definitions, the following control the SDMA: INTPND2: bit 13: SDMA Error Interrupt Pending bit 12: SDMA Normal Interrupt Pending INTCTL2: bit 13: SDMA Error Interrupt Mask. 0 = Masked 1 = Not Masked bit 12: SDMA Normal Interrupt Mask. 0 = Masked 1 = Not Masked INTSTR2 bit 13: SDMA Error Interrupt Steering.
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Intel® 413808 and 413812—SRAM DMA Unit (SDMA) 5.4 Register Definitions The SDMA controller contains separate LocalToHost (L2H) and HostToLocal (H2L) channels that are independent of each other. These are used simultaneously thus allowing full duplex transfer to occur. The location of these registers are specified as a relative offset to a 512KB aligned global PMMR offset. The default for the 512KB aligned offset is 0 FFD8 0000H defined by the PMMRBAR register. Table 298.
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SRAM DMA Unit (SDMA)—Intel® 413808 and 413812 5.4.1 LocalToHost Destination Lower Address Register - L2H_DLAR The LocalToHost Destination Lower Address Registers (L2H_DLAR) represent the lower 32-bits of the destination (host) address. Table 299.
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Intel® 413808 and 413812—SRAM DMA Unit (SDMA) 5.4.3 LocalToHost Source Lower Address Register - L2H_SLAR The LocalToHost Source Lower Address Register (L2H_SLAR) represents the lower 32 bits of the source (local) address. The upper address bits are zero, as local memory is limited to 1 Mbyte. Table 301.
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SRAM DMA Unit (SDMA)—Intel® 413808 and 413812 5.4.4 LocalToHost Byte Count Register - L2H_BCR The LocalToHost Byte Count Register (L2H_BCR) represents the byte count associated with data to be moved. Note for internal architecture reasons the byte count must be entered in two locations within this register. Table 302.
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Intel® 413808 and 413812—SRAM DMA Unit (SDMA) 5.4.5 LocalToHost Interrupt Counter/Acknowledge Register L2H_ICAR Firmware uses the LocalToHost Interrupt Counter/Acknowledge Register (L2H_ICAR) to keep track of and acknowledge interrupts. Table 303.
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SRAM DMA Unit (SDMA)—Intel® 413808 and 413812 5.4.6 LocalToHost Control/Status Register - L2H_CSR The LocalToHost Control/Status Register (L2H_CSR) provides the control and status for the LocalToHost channel. Table 304.
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Intel® 413808 and 413812—SRAM DMA Unit (SDMA) 5.4.7 LocalToHost Byte Swap Control Register - L2H_BSCR The LocalToHost Byte SWap Control Register (L2H_BSCR) provides the control to enable/disable byte swapping. The “Default” enables byte swapping. Note: Table 305.
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SRAM DMA Unit (SDMA)—Intel® 413808 and 413812 5.4.9 HostToLocal Source Upper Address Register - H2L_SUAR The HostToLocal Source Upper Address Register (H2L_SUAR) represents the upper 32-bits of the source (host) address. Table 307.
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Intel® 413808 and 413812—SRAM DMA Unit (SDMA) 5.4.11 HostToLocal Byte Count Register - H2L_BCR The HostToLocal Byte Count Registers (H2L_BCR) represent the byte count of the DMA. Table 309.
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SRAM DMA Unit (SDMA)—Intel® 413808 and 413812 5.4.12 HostToLocal Interrupt Counter/Acknowledge Register H2L_ICAR Firmware uses the HostToLocal Interrupt Acknowledge Register (H2L_ICAR) to keep track of and acknowledge interrupts. Table 310.
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Intel® 413808 and 413812—SRAM DMA Unit (SDMA) 5.4.13 HostToLocal Control/Status Register - H2L_CSR The HostToLocal Control/Status Register (H2L_CSR) provides the status and control of the HostToLocal channel. Table 311.
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SRAM DMA Unit (SDMA)—Intel® 413808 and 413812 5.4.14 HostToLocal Byte Swap Control Register - H2L_BSCR The LocalToHost Byte SWap Control Register (H2L_BSCR) provides the control to enable/disable byte swapping. The “Default” enables byte swapping. Note: Table 312.
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Intel® 413808 and 413812—SGPIO Unit 6.0 SGPIO Unit Note: For TPER mode the register interface defined here can be used. For Intel® 413808 and 413812 I/O Controllers (4138xx) non-TPER mode, see the SAS/SATA Command Summary for API to control the SGPIO units. Some limitations may apply when controlling via the API. 6.1 Overview This section describes Serial General Purpose Input Output (SGPIO) interface. The 4138xx (based on Intel XScale® technology14) supports two SGPIO interfaces.
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SGPIO Unit—Intel® 413808 and 413812 Figure 43.
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Intel® 413808 and 413812—SGPIO Unit 6.2 Theory of Operation The SGPIO is used to serialize general purpose I/O signals. For example, the initiator may want to drive multiple LEDs on the target, and thus do so by sampling and serializing the parallel initiator LED signals at a fixed sampling rate dictated by the low-to-high transition of the SLoad signal. Note that SClock is a free-running clock.
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SGPIO Unit—Intel® 413808 and 413812 6.2.3 SDataOut The SDataOut signal carries output bits associated with devices on the target. For example, on 4138xx the SGPIO can drive up to three bits per device and up to eight devices on the target, thus is able to control twenty-four outputs on the target. The SDataOut signal carries the 3-bit outputs for each device in the same order in each repeated bit stream. Figure 46.
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Intel® 413808 and 413812—SGPIO Unit 6.3 Clock Requirements 4138xx generates and drives three clock signals that are used to run the various blocks of the SGPIO units. • SClock - is the output clock of the SGPIO interface and runs at a fixed 99.8 KHz. • Load Clock - this clock is used internally to load the internal latches. This clock runs at 1/24 the SClock rate. • Blink Generator Clock - this clock is used to drive the blink generator. This clock runs at 1/12500 of the SClock rate.
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SGPIO Unit—Intel® 413808 and 413812 6.4 Output Signals Each of the 4138xx SGPIO units can support up to eight drives, and each drive can support up to three output signals. This allows the two SGPIO units on 4138xx to be able to drive up to twenty-four output signals. 4138xx supports the following output signals: • Fixed High • Protocol Engine Activity, Protocol Engine Status, or Reserved • Two programmable Blinks (A and B) In addition the outputs can be optionally inverted.
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Intel® 413808 and 413812—SGPIO Unit Figure 50. SGPIO Output OD1 Signal Output Signal ( OD1) Control bit 7 in SGODSR[0:7]x JOG Logic Inverting Logic (XOR) Control bit 6 in SGODSR[0:7]x Control bits[5:4] in SGODSR [0:7]x Fixed High Pre-Conditioning Logic FSENG Status Programmable Pattern A Programmable Pattern B B6349-01 Figure 51.
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SGPIO Unit—Intel® 413808 and 413812 6.4.1 Note: Protocol Engine Input Signals There are eight Protocol Engine activity signals (S_ACT[7:0]) and eight Protocol Engine status signals (S_STAT[7:0]) which are all input signals both SGPIO units. These Protocol Engine activity and status signals can be selected as optional output signals of the SGPIO Units that can be driven on the SDataOut pins or on the direct LED signals. Refer to Figure 49 and Figure 50 for the output selections.
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Intel® 413808 and 413812—SGPIO Unit Table 313.
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SGPIO Unit—Intel® 413808 and 413812 6.4.1.1 6.4.1.2 JOG Requirements The jog feature is optional and is controlled by the Table 328, “SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x” on page 484. When enabled, this feature monitors the input signal and if the input signal is detected low for about four seconds it will be forced high for a 250 ms duration.
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Intel® 413808 and 413812—SGPIO Unit 6.4.2 Programmable Blink Patterns Each of the SGPIO output signal supports two programmable blink patterns that can be selected using the Table 328, “SGPIO Output Data Select Register[0:7] x SGODSR[0:7]x” on page 484. The blink rate generator is clocked using an 8 Hz clock and allows the user to program a low and a high duration time using two 4-bit fields located in the Table 322, “SGPIO Programmable Blink Register x - SGPBRx” on page 476.
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SGPIO Unit—Intel® 413808 and 413812 6.5 SGPIO Unit Mode of Operations Each SGPIO unit on 4138xx can be programmed to support the following modes: • Direct LED • SGPIO 4138xx provides eight configurable pins per SGPIO unit to accommodate SGPIO mode. When the SGPIO unit is set up to operate in Direct LED mode by clearing bit[0] of Table 321, “SGPIO Interface Control Register x - SGICRx” on page 475, all eight pins provide direct LED support.
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Intel® 413808 and 413812—SGPIO Unit Example 4. SGPIO Unit 0 is in Direct LED mode supporting Drives [4,6] and SGPIO Unit 1 is in SGPIO Mode supporting Drives[1,3,5,7] In this example, SGPIO unit 0 is set up in Direct LED mode supporting Drive 4 and Drive 6. Bit[0] in Table 321, “SGPIO Interface Control Register x - SGICRx” on page 475 must be cleared for SGPIO unit 0, as this sets up the external pins for Direct LED mode.
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SGPIO Unit—Intel® 413808 and 413812 Example 5. Both SGPIO Units are used in SGPIO mode with SGPIO Unit 0 supporting Drives[0,1,3,4,5,6] and SGPIO Unit 1 supporting Drives[2,7] In this example, both SGPIO units are used and they are set up in SGPIO mode by setting bit[0] in Table 321, “SGPIO Interface Control Register x - SGICRx” on page 475. SGPIO unit 0 supports six drives.
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Intel® 413808 and 413812—SGPIO Unit 6.5.1 Note: Pin Multiplexing All S_ACT[7:0] and S_STAT[7:0] pins are multiplexed. Note that an SGPIO interface is a 4-pin interface. SGPIO unit 0 uses pins S_ACT[3:0] and S_STAT]3:0] for SGPIO signaling and direct LED controls, whereas SGPIO unit 1 uses pins S_ACT[7:4] and S_STAT[7:4] for SGPIO signaling and direct LED controls. Table 318 and Figure 322 show how the SGPIO unit 0 signals are multiplexed.
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SGPIO Unit—Intel® 413808 and 413812 supports only SAS ports has the multiplexers selecting S_ACT[x] and S_STAT[x] signals. Table 319. SGPIO Unit 1 Pin Multiplexing Note: Activity Pin Shared Pin Status Pin Shared Pin S_ACT[4] S_ACT[5] S_ACT[6] S_ACT[7] SCLOCK[1] TXRATE4[0] SDATAIN[1] TXRATE6[0] S_STAT[4] S_STAT[5] S_STAT[6] S_STAT[7] SLOAD[1] TXRATE4[1] SDATAOUT[1] TXRATE6[1] The Protocol Engine activity and status signal pairs are not connected to the corresponding SGPIO unit drive numbers.
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Intel® 413808 and 413812—SGPIO Unit 6.6 Warning: Register Definitions The SGPIO contains memory-mapped registers for: • selecting ODx output signals that are driven on the serial data bus and to direct LED pins, • reading serial data from the input data bus, • Programming Vendor Specific Code The SGPIO Units must be programmed for proper operation. By default the SGPIO units are initialized to operate in SGPIO modes. The user must program the units to place them in the desired mode of operations.
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SGPIO Unit—Intel® 413808 and 413812 6.6.1 SGPIO Interface Control Register x — SGICRx The SGPIO Interface Control Register x - SGPICRx is used to select the SGPIO unit mode of operations - SGPIO bus or direct LED interface. Each SGPIO unit can either drive eight output signals on the serial SGPIO bus or directly drive the eight output signals on eight separate pins. Table 321.
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Intel® 413808 and 413812—SGPIO Unit 6.6.2 SGPIO Programmable Blink Register x — SGPBRx This SGPIO Programmable Blink Register x - SGPBRx is used to program the programmable blink patterns. Each output signal supports two programmable blink patterns and each pattern can be programmed using two 4-bit fields. The two 4-bit fields allow the user to program a low and a high duration time.
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SGPIO Unit—Intel® 413808 and 413812 Table 322.
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Intel® 413808 and 413812—SGPIO Unit 6.6.3 SGPIO Start Drive Lower Register x — SGSDLRx The SGPIO Start Drive Lower Register x - SGSDLRx is used to program the drive outputs order as they are shifted out on the serial bit stream. For example, after the Vendor-Specific Code bits are shifted out on the SDataout pin, the user can choose in which order each drive’s outputs are shifted out. This register controls the steering of drive inputs[0:3] of the multiplexer block. Table 323.
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SGPIO Unit—Intel® 413808 and 413812 Table 323.
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Intel® 413808 and 413812—SGPIO Unit 6.6.4 SGPIO Start Drive Upper Register x — SGSDURx The SGPIO Start Drive Upper Register x — SGSDURx is used to program the drive output order as they are shifted out on the serial bit stream. For example, after the Vendor-Specific Code bits are shifted out on the SDataout pin, the user can choose in which order each drive outputs are shifted out. This register controls the steering of drive inputs[4:7] of the multiplexer block. Table 324.
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SGPIO Unit—Intel® 413808 and 413812 Table 324.
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Intel® 413808 and 413812—SGPIO Unit 6.6.5 SGPIO Serial Input Data Lower Register x — SGSIDLRx The SGPIO Serial Input Data Lower Register x - SGIDLRx is used to read the input data bits. Each drive sends three bits. This register provides the input data bits for drives 0, 1, 2, and 3. Table 325.
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SGPIO Unit—Intel® 413808 and 413812 6.6.6 SGPIO Serial Input Data Upper Register x — SGSIDURx The SGPIO Serial Input Data Upper Register x - SGIDURx is used to read the drive input data bits. Each drive sends three bits. This register provides the input data bits for drives 4, 5, 6, and 7. Table 326.
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Intel® 413808 and 413812—SGPIO Unit 6.6.8 SGPIO Output Data Select Register[0:7] x — SGODSR[0:7]x The SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x provides the bit fields to select the output signals. Each drive can support up to three output signals. Table 328.
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System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.0 System Controller (SC) and Internal Bus Bridge This chapter describes the System Controllers (SC) of the Intel® 413808 and 413812 I/O Controllers (4138xx). The System Controller controls the internal bus and its agents. There are two System Controllers on 4138xx since there are two internal busses. 7.1 Overview The System Controller controls the internal bus agents arbitrating for the internal bus.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.2 7.2.1 Theory of Operation System Controller The XSI System Controller (SC) is the arbiter for the XSI bus. There is one SC for the North XSI bus and one for the South XSI bus since there are two XSI busses on 4138xx. The XSI bus supports fully demultiplex and independent address and data paths, thus the SC performs arbitration for address requests and data requests separately. Up to 15 agents are supported by the SC.
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System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.2.2 Internal Bus Requester IDs Each of the initiator/requester on the 4138xx has an assigned unique ID, which helps identify an initiator when returning read data and for the purpose of logging transaction errors. Table 329 lists the encoded initiator IDs. Table 329.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.2.3 Parity Testing The 4138xx supports parity protections on both the 36-bit address and 128-bit data bus south internal bus. Parity is supported on a byte-wise basis. The SC provides hardware test features that allows the user to force address or data parity errors on the internal bus. This feature allows the user to test software error handling routines by forcing an address or data parity error on the internal bus.
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System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 Table 330.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.3 Internal Bus Bridge 7.3.1 Theory of Operation This section describes the internal bus bridge. The internal bus bridge isolates traffic on the north internal bus and the south internal bus. The internal bus bridge is a bidirectional bridge. Transactions targeting the south internal bus from the north internal bus are referred to as outbound transactions.
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System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.3.2 Internal Bus Commands Table 332 lists the internal bus commands that are supported on the north and south bridge interfaces. Table 332. Bridge supported Internal Bus Commands Internal Bus Command Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.3.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.3.4 Note: Bridge Memory Window The North Internal Bus interface of the Bridge performs subtractive decoding. For example, transactions on the north internal bus that are not claimed by other targets on the north internal bus are claimed by the Bridge North Interface. The South Bridge Interface performs positive decoding.
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System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.3.5 Ordering and Passing Rules Table 333 lists the ordering and passing rules requirements for the bridge. Although write requests and write data completions are completely independent transactions on the internal bus, the bridge internally combines a write request with its corresponding write data transaction when enqueuing write requests and when issuing write requests.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.3.6 Parity Support 7.3.6.1 Address Parity Generation 7.3.6.2 Address Parity Checking 7.3.6.3 7.3.6.4 The bridge supports parity as required by the south internal bus. The south internal bus supports both byte-wise address and data parity. Therefore, as a initiator the bridge is responsible to drive byte-wise parity on the south internal bus on both the 36-bit address bus and the 128-bit data bus.
PAGE 495
System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.3.7 Error Detection and Handling 7.3.7.1 Bridge North Internal Bus Interface Error The Bridge provides a set of error logging registers that are used to log any error that are encountered by the Bridge: north interface or south interface. Only one error is logged, when more errors occur when one error is already logged, the bridge would indicate that it detected more errors, but does not log these newer errors.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.3.7.2 Bridge South Internal Bus Interface Error The following conditions may be encountered by the Bridge South Interface: • Master Abort on the South Internal Bus interface. This condition may happen when the bridge attempts an address request on the south internal bus and the request is not claimed by any target. The bridge would log the error as a master abort.
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System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.4 System Controller Register Definitions The following registers are located in the Peripheral Memory-Mapped Register (PMMR) address space. They are accessible through the south internal bus accesses. The Internal Bus Arbitration Control Register provides controls for both the North and South Internal address busses.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.5 Internal Bus Bridge Register Definitions The following registers are located in the Peripheral Memory-Mapped Register (PMMR) address space. They are only accessible from the south internal bus. Accesses to the Bridge registers that originate from the north internal bus are propagated to the south internal bus, and then claimed by the Bridge on the south interface.
PAGE 499
System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.5.1 Internal Bus Arbitration Control Register — IBACR The 4138xx has two internal buses: the north internal bus and the south internal bus. Refer to the block diagram shown in Figure 2, “Intel® 413808 and 413812 I/O Controllers in TPER Mode Functional Block Diagram” on page 43. The two internal buses are identical and provide de-multiplexed address and data buses.
PAGE 500
Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge Table 334.
PAGE 501
System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.5.2 South Internal Bus Address Test Control Register — SIBATCR The SIBATCR can be used to inject an address parity error on the south internal address bus. The user must provide the ID of the initiator and also set the enable bit. The enable bit (when set) is used by hardware to inject an address parity error on the next address transaction provided the programmed ID matches.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.5.3 South Internal Bus Data Test Control Register — SIBDTCR The SIBDTCR can be used to inject a data parity error on the south internal data bus. The user must provide the ID of the initiator and also set the enable bit. The enable bit (when set) is used by hardware to inject a data parity error on the next data transaction provided the programmed ID matches. The parity error is injected in the first data phase.
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System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.5.4 Peripheral Memory-Mapped Register Base Address Register — PMMRBAR This is a 32-bit register that contains the Base or starting address of the Peripheral Memory-Mapped Register space (PMMR). The PMMR space is aligned on a 512-KByte boundary. The PMMRBAR can be used to relocate the PMMR block to any 512-KByte space of the 64 GBytes address space.
PAGE 504
Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.5.5 Determining Block Sizes for Memory Windows The memory window size can be determined by writing ones to the appropriate upper bits of the limit register. The binary-weighted value of the first non-zero bit set in the limit register indicates the size of the memory window. Table 338 describes the relationship between limit register values and the byte sizes of the memory window. Table 338.
PAGE 505
System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.5.6 Bridge Window Base Address Register — BWBAR The Bridge Base Address Register (BWBAR) defines the block of memory addresses where the Bridge Memory Window begins. The BWBAR is used in conjunction with the BWLR to form a memory window that is used by the Bridge to claim transactions on the South Internal Bus. The BWBAR defines the base address and describes the required memory block size; see Section 7.5.
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Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.5.7 Bridge Window Upper Base Address Register — BWUBAR The Bridge Window Upper Base Address Register (BWUBAR) provides the upper 4 bits of the block of memory addresses where the Bridge Memory Window begins. The BWUBAR is used in conjunction with the BWBAR to form a 36-bit base address register. Refer to the Section 7.5.6, “Bridge Window Base Address Register — BWBAR” on page 505. Table 340.
PAGE 507
System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 7.5.8 Bridge Window Limit Register — BWLR The 4138xx limit register’s (BWLR) programmed value must be naturally aligned with the base address register’s (BWBAR) programmed value. The limit register is used as a mask when the address decode for Bridge memory window is performed. Table 341. Bridge Limit Register — BWLR .
PAGE 508
Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.5.9 Bridge Error Control and Status Register — BECSR The BECSR logs the type of error that the bridge encountered on either north or south interface. Only one error can be logged at a time. The Bridge has two interrupt conditions: first Bridge error (BECSR[0]), and more than one Bridge error (BECSR[1]). When the Bridge detects an error and BECSR[0] is cleared, the error is logged in BECSR, and BECSR[0] is set to 1.
PAGE 509
System Controller (SC) and Internal Bus Bridge—Intel® 413808 and 413812 Table 342.
PAGE 510
Intel® 413808 and 413812—System Controller (SC) and Internal Bus Bridge 7.5.10 Bridge Error Address Register — BERAR This register is responsible for logging the lower 32-bit of the 36-bit address of the bridge request that encountered the error. This register is used in conjunction with the BERUAR. Refer to Section 7.5.11, “Bridge Error Upper Address Register — BERUAR” on page 510. Table 343.
PAGE 511
SRAM Memory Controller—Intel® 413808 and 413812 8.0 SRAM Memory Controller This chapter describes the integrated SRAM Memory Controller Unit (SMCU). The operating modes, initialization, and implementation are detailed in this chapter. 8.1 Overview The Intel® 413808 and 413812 I/O Controllers in TPER Mode (4138xx integrates a high performance, multi-ported SRAM Memory Controller to provide access to the on-chip 1.0 MByte SRAM Memory. The SRAM Memory Controller supports: • 1.
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Intel® 413808 and 413812—SRAM Memory Controller 8.2 Glossary This section lists commonly used terms throughout this chapter: Table 345. Commonly Used Terms Term Definition Once an error is detected within the memory array, the SMCU must correct the error (if Scrubbing possible) while delivering the data to the initiator. Correcting the memory location is referred to as “scrubbing the array.” The SMCU relies on software to scrub any errors.
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SRAM Memory Controller—Intel® 413808 and 413812 8.3 Theory of Operation 8.3.1 Functional Block The 4138xx SRAM memory controller translates transactions from the north internal bus into the protocol supported by the SRAM memory subsystem. The SRAM memory controller logically comprises the blocks illustrated in Figure 56. The SMCU supports a separate read and write port. Figure 56.
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Intel® 413808 and 413812—SRAM Memory Controller 8.3.1.2 Address Decode Blocks 8.3.1.2.1 SRAM Memory Array Space 8.3.1.2.2 Memory-Mapped Register Space 8.3.1.2.3 North Internal Bus Port Address Decode 8.3.1.3 Memory Transaction Queues 8.3.1.3.1 North Internal Bus Port Transaction Queue (NIBPTQ) 8.3.1.4 Configuration Registers Address Decode is performed for transactions from input North Internal Bus port to determine if the SMCU should claim the transaction.
PAGE 515
SRAM Memory Controller—Intel® 413808 and 413812 8.3.1.5.2 Error Correction Logic The Error Correction Logic generates the ECC code for SRAM reads and writes. For reads, this logic compares the ECC codes read with the locally generated ECC code. If the codes mismatch then the Error Correction Logic determines the error type. For a single-bit error, this block determines which bit is in error and corrects the error.
PAGE 516
Intel® 413808 and 413812—SRAM Memory Controller 8.3.1.6 8.3.1.7 North Internal Bus Port Transaction Ordering Since requests from the north internal bus port are queued in the NIBPTQ, the port needs to maintain order of requests addressing the SRAM. Coherency between the north internal bus port and the other ports are maintained by the SMCU as described in “SMCU Port Coherency” below. SMCU Port Coherency With the queueing of SRAM transactions in multiple ports, coherency of memory must be maintained.
PAGE 517
SRAM Memory Controller—Intel® 413808 and 413812 8.3.2 SRAM Memory Interface Support 8.3.2.1 SRAM Initialization 8.3.2.2 SRAM Read Sequence The 4138xx memory controller supports 1.0 Mbytes of on-chip SRAM. The SMCU supports a 256-bit data bus width memory with ECC. The SMCU supports 7-bit ECC on every 32-bit data quantity, providing higher performance when the core processor is processing data by eliminating any RMW cycle required for 4-Byte store ECC generation.
PAGE 518
Intel® 413808 and 413812—SRAM Memory Controller 8.3.2.3 SRAM Write Sequence Write transactions require ECC codes to be generated and stored in the SRAM array with the data being written. The behavior is different depending on the size of the data being written. Section 8.3.3, “Error Correction and Detection” on page 519 explains the ECC algorithm in more detail. 1. Each of the SMCU inbound memory transaction ports decodes the address to determine if the transaction should be claimed.
PAGE 519
SRAM Memory Controller—Intel® 413808 and 413812 8.3.3 Error Correction and Detection The SMCU is capable of correcting any single bit errors and detecting any double bit errors in the 4138xx SRAM memory subsystem. ECC enhances the reliability of a memory subsystem by correcting single bit errors caused by electrical noise or occasional alpha particle hits on the SRAM memory array.
PAGE 520
Intel® 413808 and 413812—SRAM Memory Controller 8.3.3.1 ECC Generation For write operations, the SMCU generates the error correction code which is written along with the data. This section describes the operation of the SRAM Control Block for ECC generation on 32-bit data of the 256-bit wide memory. The SMCU will generate 7-bit wide ECC on every 32-bit data.
PAGE 521
SRAM Memory Controller—Intel® 413808 and 413812 8.3.3.2 ECC Generation for Partial Writes Figure 58.
PAGE 522
Intel® 413808 and 413812—SRAM Memory Controller 8.3.3.3 ECC Checking The ECC logic uses the following ECC read algorithm. This algorithm corrects the data before it's driven onto the internal bus.
PAGE 523
SRAM Memory Controller—Intel® 413808 and 413812 Figure 59 shows how the data flows through the ECC hardware for a read transaction. Figure 59.
PAGE 524
Intel® 413808 and 413812—SRAM Memory Controller Figure 60 illustrates the H-Matrix used for decoding the syndrome. For single-bit errors, the H-Matrix indicates the bit that contains the error and consequently, which bit to fix. Figure 60.
PAGE 525
SRAM Memory Controller—Intel® 413808 and 413812 Referring to Figure 59, the syndrome bits are created by XORing the ECC code bits as indicated by the appropriate row of the G-Matrix in Figure 58 with the corresponding ECC bits read from memory. For example, the SMCU derives syndrome bit 0 by XORing ECC code associated with data bits 0, 2, 5, 8…15, 17, 20, 22, 24, 26, 28 and ECC bit 0 (physically read on SCB[0]). The SMCU performs seven such XOR operations (one per syndrome bit).
PAGE 526
Intel® 413808 and 413812—SRAM Memory Controller 8.3.3.4 Note: 8.3.3.4.1 Note: Scrubbing Fixing the data error in memory is called scrubbing. The 4138xx relies on Intel XScale® processor software to perform the scrubbing. When the SMCU detects an error during a read, the SMCU logs the address where the error occurred and interrupts the core. The core decides how to fix the error through an interrupt handler.
PAGE 527
SRAM Memory Controller—Intel® 413808 and 413812 8.3.3.5 ECC Disabled 8.3.3.6 ECC Testing If software disables ECC, the SMCU does generate the ECC byte for writes, but does not check the ECC byte for reads. Section 8.3.3.4, “Scrubbing” on page 526 explains how software is responsible for correcting an error in the memory array once it has been detected by the ECC logic. The SMCU implements the SECTST register providing the programmer the ability to test error handling software.
PAGE 528
Intel® 413808 and 413812—SRAM Memory Controller 8.3.4 Byte Parity Checking and Generation All the direct memory ports of the SMCU supports byte-wise parity on the data bus.
PAGE 529
SRAM Memory Controller—Intel® 413808 and 413812 8.3.4.1 Note: Parity Generation The direct memory port interface of the SMCU only generates data parity before delivering data onto the port. After the requested data is read from memory and ECC has been verified, the direct memory port interface generates even data parity before delivering the data on the direct memory port. Table 347 lists the data bytes that are used for data parity calculation.
PAGE 530
Intel® 413808 and 413812—SRAM Memory Controller 8.3.4.2 Note: Parity Checking The direct memory port interface of the SMCU only checks data parity while receiving data. The direct memory port interface verifies data parity on the port interface, and then generates ECC before writing the data to memory. Table 347 lists the data bits that are used for the parity calculation. The parity bits are calculated by bit XORing the data bits as shown in Table 347.
PAGE 531
SRAM Memory Controller—Intel® 413808 and 413812 8.4 ECC Interrupts/Error Conditions The SMCU has two ECC conditions which require intervention from the Intel XScale® processor. If a single-bit error is detected during a read cycle, the SMCU can correct the data returned but software needs to fix the error in the memory array. If a multi-bit error is detected, the core decides how to handle the condition.
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Intel® 413808 and 413812—SRAM Memory Controller 8.4.1 Single-Bit Error Detection When enabled, the SMCU interrupts the core when the ECC logic detects a single-bit error by setting the appropriate bit in the MCISR register. The core knows the interrupt was caused by a single-bit error by polling the SELOG register. The SRAM Control Block ensures that correct data is returned but the interrupt handler is responsible for scrubbing the error in the array (refer to Section 8.3.3.4, “Scrubbing” on page 526).
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SRAM Memory Controller—Intel® 413808 and 413812 8.4.2 Multi-bit Error Detection If a multi-bit error occurs during a read or write transaction and error reporting is enabled, the SMCU sets SMCISR[0] which asserts an interrupt to the core. Upon receiving an interrupt, the core knows the interrupt was caused by a multi-bit error by polling the SELOG registers.
PAGE 534
Intel® 413808 and 413812—SRAM Memory Controller 8.5 Parity Interrupts/Error Conditions If a data parity error is detected on any of the SMCU ports and parity is enabled, the SMCU records the requesting port that detected the parity error in the SPCSR[19:16] and interrupts the core. Refer to the Section 8.6.8, “SRAM Parity Control and Status Register — SPARCSR” on page 542 When the SMCU detects a parity error, the SMCISR[8] is set to 1.
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SRAM Memory Controller—Intel® 413808 and 413812 8.6 Note: Register Definitions A series of configuration registers control the SMCU. Software can determine the status of the SMCU by reading the status registers. Table 349 lists all of the SMCU registers which are detailed further in proceeding sections. Constant polling of SMCU MMRs can result in inducing long latencies in peripheral unit SRAM transactions, and therefore may negatively impact performance. Polling of SMCU MMRs should be avoided.
PAGE 536
Intel® 413808 and 413812—SRAM Memory Controller 8.6.1 SRAM Base Address Register — SRAMBAR This register indicates the lower twelve bits of the beginning address (base address) of SRAM memory array space. The SRAM is addressed using a 36-bit address. This register is used in conjunction with the Section 8.6.2, SRAM Upper Base Address Register — SRAMUBAR. After reset the default starting address of the SRAM memory is 0 FFE0 0000H. SRAM memory space must never cross a 1 Mbyte boundary. Note: Table 350.
PAGE 537
SRAM Memory Controller—Intel® 413808 and 413812 • Disable single-bit error reporting • Enable single-bit error correcting For more details, see Section 8.3.3, “Error Correction and Detection” on page 519 and Section 8.4, “ECC Interrupts/Error Conditions” on page 531. Table 352.
PAGE 538
Intel® 413808 and 413812—SRAM Memory Controller 8.6.4 SRAM ECC Log Register — SELOGR The SRAM ECC Log Register is responsible for logging the error types detected on the local memory bus. One error can be detected and logged. The error type is logged (single-bit or multi-bit) along with the syndrome that indicated the error. For a single-bit error, software can read this syndrome and determine which bit had the error in order to perform scrubbing.
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SRAM Memory Controller—Intel® 413808 and 413812 Table 353.
PAGE 540
Intel® 413808 and 413812—SRAM Memory Controller 8.6.5 SRAM ECC Address Register — SEAR This register is responsible for logging the address where the error was detected on the local memory bus. One error can be detected and logged. The software knows which SRAM address had the error by reading this register and decoding the syndrome in the log register. The upper 4 bits are captured in the SECR — refer to Section 8.6.3, SRAM ECC Control Register — SECR. For error details, see Section 8.3.
PAGE 541
SRAM Memory Controller—Intel® 413808 and 413812 8.6.7 SRAM ECC Test Register — SECTST This register allows testing between the SRAM ECC logic and the memory subsystem (Section 8.3.3.6, “ECC Testing” on page 527). To test error handling software, the programmer writes this register with a non-zero masking function. Any subsequent writes to memory stores a masked version of the computed ECC. Therefore, any subsequent reads to these locations result in an ECC error. Table 356.
PAGE 542
Intel® 413808 and 413812—SRAM Memory Controller 8.6.8 SRAM Parity Control and Status Register — SPARCSR This register programs the SMCU parity checking capabilities. This register is also responsible for logging the error types detected on the SMCU memory ports. Only one error can be detected and logged. The error recorded corresponds to the addresses in (SPAR, SPUAR) and (SPCAR, SPCUAR). The status bits are read-only bits and only have meaning if SMCISR[8] is non-zero. For more details, see Section 8.3.
PAGE 543
SRAM Memory Controller—Intel® 413808 and 413812 8.6.9 SRAM Parity Address Register — SPAR This register is responsible for logging the lower 32-bit address of where the error was detected on the SMCU memory ports. Note that the address is 36-bit. This register is used in conjunction with the Section 8.6.10, “SRAM Parity Upper Address Register — SPUAR” on page 543. One error can be detected and logged.
PAGE 544
Intel® 413808 and 413812—SRAM Memory Controller 8.6.11 SRAM Memory Controller Interrupt Status Register — SMCISR Setting®the SMCISR asserts an interrupt to the core. Upon an interrupt, the Intel XScale processor polls the interrupt status register for each unit. The interrupt status register tells the core the reason for the interrupt.
PAGE 545
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.0 Peripheral Bus Interface Unit This chapter describes the Peripheral Bus Interface Unit (PBI) of the Intel® 413808 and 413812 I/O Controllers in TPER Mode (4138xx).
PAGE 546
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.1 Note: Overview The Peripheral Bus Interface Unit (PBI) is a data communication path to the flash memory components and peripherals of a 4138xx hardware system. The PBI allows the processor to read and write data to these supported flash components and other peripherals. To perform these tasks at high bandwidth, the PBI bus features a burst read transfer capability which allows successive data transfers for multi-byte read requests.
PAGE 547
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.2 Peripheral Bus Signals 9.2.1 Address Signal Definitions 9.2.2 Data Signal Definitions 9.2.3 Control/Status Signal Definitions Note: Bus signals consist of three groups: • address • data • control/status The address signal group A[24:0] consists of 25 lines which allows the PBI to address up to 32 MBytes per peripheral device. During and address cycle (TA), the processor drives A[24:0] with the starting address of the bus access.
PAGE 548
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.2.4 Bus Width Each address range’s attributes are programmed in the PBIs boundary registers. The PBI allows an 8-, or 16-bit data bus width for each range. The PBI places 8- and 16-bit data on low-order data signals, simplifying the interface to narrow bus external devices. As shown in Figure 63, 8-bit data is placed on lines D[7:0]; 16-bit data is placed on lines D[15:0]. Figure 63.
PAGE 549
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.2.5 Detailed Signal Descriptions Bus signal descriptions are detailed in Table 362. Table 361. Bus Signal Descriptions NAME DESCRIPTION DATA BUS carries 16-bit physical addresses and 8-, or 16-bit data to and from memory. D[15:0] A[24:0] POE# PCE[1:0]# PWE# PB_RSTOUT# October 2007 Order Number: 317805-001US During a data (Td) cycle, bits 0-7, or 0-15 contain read or write data, depending on the corresponding bus width.
PAGE 550
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.2.6 Flash Memory Support Note: Be sure to refer to the System Software Architecture Specification and Design Guide for details on supported Flash parts, since the Transport Firmware must provide support for the Flash device in addition to PBI. PBI peripheral bus interface supports 8-, or 16- bit Flash devices. The PBI provides programmable wait state functionality for peripheral memory windows.
PAGE 551
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.2.6.1 Flash Read Cycle Reading a Flash device involves driving the address, output enable, and chip enable. Depending on the speed of the Flash device, the data returns several cycles later. The definition of address-to-data wait states are the number of cycles between the assertion of PCE[1:0]#, and the arrival of data from the Flash device on D[7:0] (8-bit Flash).
PAGE 552
Intel® 413808 and 413812—Peripheral Bus Interface Unit Figure 66 illustrates a burst read cycle example for a 120 ns Flash device. This example is illustrating a burst of two bytes or words. The PBI is capable of bursting up to four bytes or words. The number of wait states used for address-to-data and data-to-data are provided by the Address-to-Data Wait States and the Data-to-Data Wait States field in PBBARx respectively. Figure 66.
PAGE 553
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.2.6.2 Flash Write Cycle Address-to-data and recovery wait states for reads and writes are identical and programmed in PBBAR0 and PBBAR1. Refer to Table 362 for the programmable address-to data wait states. However, Any write transactions issued to a Peripheral address space window must always represent a single peripheral bus data cycle (strb, strh) depending on the bus width selected in PBBAR0 — PBBAR1.
PAGE 554
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.3 Register Definitions A series of configuration registers control PBI. Software can determine PBI status by reading the status register. Table 363 lists all PBI registers which are detailed further in proceeding sections. Table 363. Peripheral Bus Interface Registers Section, Register Name — Acronym (Page) Section 9.3.1, “PBI Control Register — PBCR” on page 555 Section 9.3.2, “PBI Status Register — PBISR” on page 555 Section 9.3.
PAGE 555
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.3.1 PBI Control Register — PBCR The PBI Control Register (PBCR) is responsible for enabling operation of PBI state machines. Table 364.
PAGE 556
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.3.3 Determining Block Sizes for Memory Windows The memory window size can be determined by writing ones to the appropriate upper bits of the limit register. The binary-weighted value of the first non-zero bit set in the limit register indicates the size of the memory window. Table 366 describes the relationship between limit register values and the byte sizes of the memory window. Table 366.
PAGE 557
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.3.4 PBI Base Address Register 0 — PBBAR0 The PBI Base Address Register 0 (PBBAR0) defines the block of memory addresses where PBI Memory Window 0 begins. The PBBAR0 defines the base address and describes the required memory block size; see Section 9.3.3, “Determining Block Sizes for Memory Windows” on page 556. The selected base address needs to be naturally aligned to the granularity of the memory block size.
PAGE 558
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.3.5 PBI Limit Register 0 — PBLR0 The 4138xx limit register’s (PBLR0) programmed value must be naturally aligned with the base address register’s (PBBAR0) programmed value. The limit register is used as a mask when the address decode for memory window 0 is performed. Table 368. PBI Limit Register 0 — PBLR0 .
PAGE 559
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.3.6 PBI Base Address Register 1 — PBBAR1 The PBI Base Address Register 1 (PBBAR1) defines the block of memory addresses where PBI Memory Window 1 begins. The PBBAR1 defines the base address and describes the required memory block size; see Section 9.3.3, “Determining Block Sizes for Memory Windows” on page 556. The selected base address needs to be naturally aligned to the granularity of the memory block size.
PAGE 560
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.3.7 PBI Limit Register 1 — PBLR1 The 4138xx limit register (PBLR1) and base address register (PBBAR1) programmed values must be naturally aligned. The limit register is used as a mask when the address decode for memory window 1 is performed. Table 370. PBI Limit Register 1 — PBLR1 .
PAGE 561
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.3.8 PBI Drive Strength Control Register — PBDSCR This register is used to manually control slew rate and drive strength for all of 4138xx pins with the exception of high-speed serial interfaces, the SDRAM interface, and the PCI-X interface. By default, this register is not required to program. This register should not be programmed to a different value without consulting the 4138xx where the appropriate values are specified. Note: Table 371.
PAGE 562
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.3.9 Processor Frequency Register - PFR This register indicates the clock frequencies of the Intel XScale® processor and the internal buses of the 4138xx. For products with two enabled Intel XScale® processors, the cores run at the same clock frequency. Table 372.
PAGE 563
Peripheral Bus Interface Unit—Intel® 413808 and 413812 9.3.10 External Strap Status Register 0 — ESSTSR0 The External Strap Status Register 0 provides software a way to read the states of the current settings of the straps. Refer to the Clock and Reset Chapter for external strap descriptions. Table 373.
PAGE 564
Intel® 413808 and 413812—Peripheral Bus Interface Unit 9.3.11 Unique ID Register 0 — UID0 The Unique ID register 0 represents a 28-bit unique value. Table 374.
PAGE 565
Interrupt Controller Unit—Intel® 413808 and 413812 10.0 Interrupt Controller Unit This chapter describes the Intel® 413808 and 413812 I/O Controllers in TPER Mode(4138xx) Interrupt Controller Unit. Operation modes, setup, external memory interface, and implementation of interrupts are described in this chapter. infrastructure 10.1 Overview The interrupt control unit manages interrupt routing and interrupt sources to the Intel XScale® processor.
PAGE 566
Intel® 413808 and 413812—Interrupt Controller Unit 10.2 10.2.1 Theory of Operation Interrupt Controller Unit The 4138xx Interrupt®Controller Unit (ICU) provides the ability to generate interrupts to both the Intel XScale processor and the PCI interrupt pins. In addition to the® internal peripherals, external devices may also generate interrupts to the Intel XScale processor. External devices can generate interrupts via the XINT[15:0]# pin and the HPI# pin.
PAGE 567
Interrupt Controller Unit—Intel® 413808 and 413812 10.3 The Intel XScale® Processor Exceptions Architecture The Intel XScale® processor supports five types of exceptions16, and a privileged processing mode for each type.
PAGE 568
Intel® 413808 and 413812—Interrupt Controller Unit 10.3.3 Exception Priorities and Vectors It is important to note that fast interrupt (FIQ) is higher priority than the normal interrupt (IRQ). In addition, while an FIQ exception is executing, the IRQ exception is masked out. When an exception is taken by the processor, the Program Counter (PC) is loaded with the vector associated with that exception as specified by Table 376.
PAGE 569
Interrupt Controller Unit—Intel® 413808 and 413812 10.4 Intel® 413808 and 413812 I/O Controllers in TPER Mode External Interrupt Interface The interrupt controller attached to the Intel XScale® processor has the facilities necessary to handle all core processor and peripheral internal interrupts as well as the sixteen external interrupts (XINT[15:0]#) and a high priority interrupt (HPI#). The 4138xx Primary PCI local bus interface includes four interrupt output signals (XINT[3:0]#/P_INT[D:A]#).
PAGE 570
Intel® 413808 and 413812—Interrupt Controller Unit The external interrupt input interface for the 4138xx consists of the pins shown in Table 377. Table 377. Interrupt Input Pin Descriptions Signal Description This is a bi-directional pin. When 4138xx is setup as an endpoint with the PCI-X interface, this pin acts as an output pin (P_INTA#). This pin can act as an input (XINT0#) and drive the XINT0# input of the Interrupt Controller.
PAGE 571
Interrupt Controller Unit—Intel® 413808 and 413812 10.4.2 Outbound Interrupts When 4138xx is setup as an endpoint device with the PCI-X interface, the XINT[3:0]# pins act as output pins (P_INT[D:A]#) respectively. The Messaging Unit (MU) and the TPMI functions have the capability of generating interrupts on the PCI interrupt output pins. The MU has two distinct messaging mechanisms.
PAGE 572
Intel® 413808 and 413812—Interrupt Controller Unit 10.5 The Intel® 413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Unit The 4138xx Interrupt Controller Unit (ICU) provides a flexible, low-latency means for requesting interrupts and minimizing the core’s interrupt handling burden. All interrupt sources are combined into one of the two internal interrupt exceptions: IRQ and FIQ.
PAGE 573
Interrupt Controller Unit—Intel® 413808 and 413812 10.5.1 Programmer Model 10.5.1.1 Active Interrupt Source Control and Status Software has access to 15 registers in the ICU. These registers control, masking, prioritization, and vector generation for all interrupt sources. The INTCTL[3:0] are used to enable or disable (mask) individual interrupts. As mentioned, masking of all interrupts may still be accomplished via the CPSR register in the core.
PAGE 574
Intel® 413808 and 413812—Interrupt Controller Unit The INTBASE and INTSIZE registers are used to establish a contiguous Interrupt Service Routine (ISR) memory range for all of 128 possible sources. The architecture provides for an ISR ranging from 4 bytes to 64 Kbytes per source. The actual vector value is a function of the INTBASE and the INTSIZE registers and is based on a fixed order of all 128 possible interrupt sources. The vectors begin at INTBASE with source 0 (i.e.
PAGE 575
Interrupt Controller Unit—Intel® 413808 and 413812 10.5.2 Operational Blocks The ICU provides the connections to the Intel XScale® processor. These connections are shown in Figure 70. Figure 70.
PAGE 576
Intel® 413808 and 413812—Interrupt Controller Unit 10.5.3 Intel® 413808 and 413812 I/O Controllers in TPER Mode: Internal Peripheral Interrupt The 4138xx Interrupt Controller receives inputs from multiple internal interrupt sources. All pending interrupts required during normal operation of the various peripheral units are available in either the IINTSRC[3:0] or FINTSRC[3:0] registers depending on the value in INTSTR[3:0].
PAGE 577
Interrupt Controller Unit—Intel® 413808 and 413812 10.5.3.1 Note: Normal Interrupt Sources The 4138xx Interrupt Controller receives normal interrupts from the Application DMA channels, Performance Monitoring Unit, the I2C Bus Interface Unit, the ATUE, the ATUX, the Programmable Timers, the Messaging Unit and the UARTs. The Application DMA channel interrupts for End of Transfer interrupt or End of Chain interrupt are demultiplexed into the interrupt controller.
PAGE 578
Intel® 413808 and 413812—Interrupt Controller Unit 10.5.3.2 Error Interrupt Sources The 4138xx Interrupt Controller receives error interrupts from the ATUs, the Messaging Unit. Each of these interrupts represent an error condition in the peripheral unit. Refer to the appropriate units for more details. A valid interrupt from any of these sources, outputs a level-sensitive interrupt to the 4138xx Interrupt Controller input.
PAGE 579
Interrupt Controller Unit—Intel® 413808 and 413812 10.5.4 High-Priority Interrupt (HPI#) 10.5.5 Timer Interrupts 10.5.6 Inter-Processor Interrupts Note: IPIs are not supported on 4138xx. The HPI# pin generates an interrupt for implementation of critical interrupt routines. Each of the two timer units has an associated interrupt. Timer interrupts are connected directly to the 4138xx interrupt controller and are posted in either the IINTSRC[3:0] or FINTSRC[3:0] registers.
PAGE 580
Intel® 413808 and 413812—Interrupt Controller Unit 10.6 Default Status The interrupt logic is reset by the PCI reset signal or through software. Table 381 shows the power-up and reset values. Table 381. Default Interrupt Routing and Status Values Register Default Value Description INTCTL0 0000 0000H All interrupts 31:0 masked. INTCTL1 0000 0000H All interrupts 63:32 masked. INTCTL2 0000 0000H All interrupts 95:64 masked. INTCTL3 0000 0000H All interrupts 127:96 masked.
PAGE 581
Interrupt Controller Unit—Intel® 413808 and 413812 10.7 Interrupt Control Unit Registers All Interrupt Controller registers are visible as 4138xx memory mapped registers and can be accessed through the internal®memory bus. Each is a 32-bit register and is memory-mapped in the Intel XScale processor memory space. The programmer interface to the interrupt controller is through the coprocessor registers. Table 382 describes these registers.
PAGE 582
Intel® 413808 and 413812—Interrupt Controller Unit Table 382.
PAGE 583
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.1 Interrupt Base Register — INTBASE The Interrupt Base Register indicates the beginning of the Interrupt Service Routine (ISR) memory range that contains the interrupt service routines for up to 128 sources. The starting address must be on a boundary equal to the granularity of the ISR memory range as specified by the INTSIZE registers.
PAGE 584
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.2 Interrupt Size Register — INTSIZE The Interrupt Size Register indicates the size of the Interrupt Service Routine (ISR) memory range that contains the interrupt service routines for up to 128 sources. The INTSIZE register can allocate from 4 bytes to 64 Kbytes of memory address space for the ISR per source. This means that the INTSIZE register can allocate a total ISR memory space that ranges in size from 512 bytes to 8 Mbytes.
PAGE 585
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.3 IRQ Interrupt Vector Register — IINTVEC The IRQ Interrupt Vector Register is a 32-bit Coprocessor 6 control register. Following an IRQ exception, the IRQ interrupt service routine reads the 32-bit vector to the ISR for the active IRQ source with the highest priority. The actual vector value is a function of the INTBASE and the INTSIZE registers and is based on a fixed order of all 128 possible interrupt sources.
PAGE 586
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.4 FIQ Interrupt Vector Register — FINTVEC The FIQ Interrupt Vector Register is a 32-bit Coprocessor 6 control register. Following an FIQ exception, the FIQ interrupt service routine reads the 32-bit vector to the ISR for the active FIQ source with the highest priority. The actual vector value is a function of the INTBASE and the INTSIZE registers and is based on a fixed order of all 128 possible interrupt sources.
PAGE 587
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.5 Interrupt Pending Register 0 — INTPND0 The Interrupt Pending register 0 is a 32-bit Coprocessor 6 control register that can be used to verify pending interrupts. Software can use this registers to poll interrupts as this register is located before the INTCTL0 mask Register. Table 387.
PAGE 588
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.6 Interrupt Pending Register 1 — INTPND1 The Interrupt Pending register 0 is a 32-bit Coprocessor 6 control register that can be used to verify pending interrupts. Software can use this registers to poll interrupts as this register is located before the INTCTL1 mask Register. Table 388.
PAGE 589
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.7 Interrupt Pending Register 2 — INTPND2 The Interrupt Pending register 0 is a 32-bit Coprocessor 6 control register that can be used to verify pending interrupts. Software can use this registers to poll interrupts as this register is located before the INTCTL2 mask Register. Table 389.
PAGE 590
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.8 Interrupt Pending Register 3 — INTPND3 The Interrupt Pending register 3 is a 32-bit Coprocessor 6 control register that can be used to verify pending interrupts. Software can use this registers to poll interrupts as this register is located before the INTCTL3 mask Register. Table 390.
PAGE 591
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.9 Interrupt Control Register 0 — INTCTL0 The Interrupt Control register 0 is a 32-bit Coprocessor 6 control register used to specify which of 32 interrupts are masked. Table 391.
PAGE 592
Intel® 413808 and 413812—Interrupt Controller Unit Table 391.
PAGE 593
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.10 Interrupt Control Register 1 — INTCTL1 The Interrupt Control register 1 is a 32-bit Coprocessor 6 control register used to specify which of 32 interrupts are masked. Table 392.
PAGE 594
Intel® 413808 and 413812—Interrupt Controller Unit Table 392.
PAGE 595
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.11 Interrupt Control Register 2 — INTCTL2 The Interrupt Control register 2 is a 32-bit Coprocessor 6 control register used to specify which of 32 interrupts are masked. Table 393.
PAGE 596
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.12 Interrupt Control Register 3 — INTCTL3 The Interrupt Control register 3 is a 32-bit Coprocessor 6 control register used to specify which of 32 interrupts are masked. Table 394.
PAGE 597
Interrupt Controller Unit—Intel® 413808 and 413812 Table 394.
PAGE 598
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.13 Interrupt Steering Register 0 — INTSTR0 The Interrupt Steering Register 0 allows system designers to direct any of 32 internal or external interrupt sources to either one of the two internal interrupt exceptions, FIQ and IRQ. When an interrupt is enabled with the INTCTL0 register, this register steers the interrupt to an internal interrupt exception. Table 395.
PAGE 599
Interrupt Controller Unit—Intel® 413808 and 413812 Table 395.
PAGE 600
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.14 Interrupt Steering Register 1 — INTSTR1 The Interrupt Steering Register 1 allows system designers to direct any of 32 internal or external interrupt sources to either one of the two internal interrupt exceptions, FIQ and IRQ. When an interrupt is enabled with the INTCTL1 register, this register steers the interrupt to an internal interrupt exception. Table 396.
PAGE 601
Interrupt Controller Unit—Intel® 413808 and 413812 Table 396.
PAGE 602
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.15 Interrupt Steering Register 2 — INTSTR2 The Interrupt Steering Register 2 allows system designers to direct any of 32 internal or external interrupt sources to either one of the two internal interrupt exceptions, FIQ and IRQ. When an interrupt is enabled with the INTCTL2 register, this register steers the interrupt to an internal interrupt exception. Table 397.
PAGE 603
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.16 Interrupt Steering Register 3 — INTSTR3 The Interrupt Steering Register 3 allows system designers to direct any of 32 internal or external interrupt sources to either one of the two internal interrupt exceptions, FIQ and IRQ. When an interrupt is enabled with the INTCTL3 register, this register steers the interrupt to an internal interrupt exception. Table 398.
PAGE 604
Intel® 413808 and 413812—Interrupt Controller Unit Table 398.
PAGE 605
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.17 IRQ Interrupt Source Register 0 — IINTSRC0 The IRQ Interrupt Source register is a 32-bit Coprocessor 6 control register used to specify which of 32 interrupts that are steered to the internal IRQ exception are unmasked by the INTCTL0 register and active. The INTSTR0 control register is used to steer individual interrupts to the IRQ exception.
PAGE 606
Intel® 413808 and 413812—Interrupt Controller Unit Table 399.
PAGE 607
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.18 IRQ Interrupt Source Register 1 — IINTSRC1 The IRQ Interrupt Source register is a 32-bit Coprocessor 6 control register used to specify which of 32 interrupts that are steered to the internal IRQ exception are unmasked by the INTCTL1 register and active. The INTSTR1 control register is used to steer individual interrupts to the IRQ exception.
PAGE 608
Intel® 413808 and 413812—Interrupt Controller Unit Table 400.
PAGE 609
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.19 IRQ Interrupt Source Register 2 — IINTSRC2 The IRQ Interrupt Source register is a 32-bit Coprocessor 6 control register used to specify which of 32 interrupts that are steered to the internal IRQ exception are unmasked by the INTCTL2 register and active. The INTSTR2 control register is used to steer individual interrupts to the IRQ exception.
PAGE 610
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.20 IRQ Interrupt Source Register 3 — IINTSRC3 The IRQ Interrupt Source register is a 32-bit Coprocessor 6 control register used to specify which of 32 interrupts that are steered to the internal IRQ exception are unmasked by the INTCTL3 register and active. The INTSTR3 control register is used to steer individual interrupts to the IRQ exception.
PAGE 611
Interrupt Controller Unit—Intel® 413808 and 413812 Table 402.
PAGE 612
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.21 FIQ Interrupt Source Register 0 — FINTSRC0 The FIQ Interrupt Source register 0 is a 32-bit Coprocessor 6 control register used to specify which interrupts that are steered to the internal FIQ exception are unmasked by the INTCTL0 register and active. The INTSTR0 control register is used to steer individual interrupts to the FIQ exception.
PAGE 613
Interrupt Controller Unit—Intel® 413808 and 413812 Table 403.
PAGE 614
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.22 FIQ Interrupt Source Register 1 — FINTSRC1 The FIQ Interrupt Source register 1 is a 32-bit Coprocessor 6 control register used to specify which interrupts that are steered to the internal FIQ exception are unmasked by the INTCTL1 register and active. The INTSTR1 control register is used to steer individual interrupts to the FIQ exception.
PAGE 615
Interrupt Controller Unit—Intel® 413808 and 413812 Table 404.
PAGE 616
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.23 FIQ Interrupt Source Register 2 — FINTSRC2 The FIQ Interrupt Source register 2 is a 32-bit Coprocessor 6 control register used to specify which interrupts that are steered to the internal FIQ exception are unmasked by the INTCTL2 register and active. The INTSTR2 control register is used to steer individual interrupts to the FIQ exception.
PAGE 617
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.24 FIQ Interrupt Source Register 3 — FINTSRC3 The FIQ Interrupt Source register 3 is a 32-bit Coprocessor 6 control register used to specify which interrupts that are steered to the internal FIQ exception are unmasked by the INTCTL3 register and active. The INTSTR3 control register is used to steer individual interrupts to the FIQ exception.
PAGE 618
Intel® 413808 and 413812—Interrupt Controller Unit Table 406.
PAGE 619
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.25 Interrupt Priority Register 0 — IPR0 The Interrupt Priority Register 0 is a 32-bit Coprocessor 6 control register used to assign a priority level to interrupt sources 15 down to 0.
PAGE 620
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.26 Interrupt Priority Register 1 — IPR1 The Interrupt Priority Register 1 is a 32-bit Coprocessor 6 control register used to assign a priority level to interrupt sources 31 down to 15.
PAGE 621
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.27 Interrupt Priority Register 2 — IPR2 The Interrupt Priority Register 2 is a 32-bit Coprocessor 6 control register used to assign a priority level to interrupt sources 47 down to 32.
PAGE 622
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.28 Interrupt Priority Register 3 — IPR3 The Interrupt Priority Register 3 is a 32-bit Coprocessor 6 control register used to assign a priority level to interrupt sources 63 down to 48.
PAGE 623
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.29 Interrupt Priority Register 4 — IPR4 The Interrupt Priority Register 4 is a 32-bit Coprocessor 6 control register used to assign a priority level to interrupt sources 79 down to 64.
PAGE 624
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.30 Interrupt Priority Register 5 — IPR5 The Interrupt Priority Register 5 is a 32-bit Coprocessor 6 control register used to assign a priority level to interrupt sources 95 down to 80.
PAGE 625
Interrupt Controller Unit—Intel® 413808 and 413812 10.7.31 Interrupt Priority Register 6 — IPR6 The Interrupt Priority Register 6 is a 32-bit Coprocessor 6 control register used to assign a priority level to interrupt sources 111 down to 96.
PAGE 626
Intel® 413808 and 413812—Interrupt Controller Unit 10.7.32 Interrupt Priority Register 7 — IPR7 The Interrupt Priority Register 7 is a 32-bit Coprocessor 6 control register used to assign a priority level to interrupt sources 127 down to 112.
PAGE 627
Timers—Intel® 413808 and 413812 11.0 Timers This chapter describes the Intel XScale® processor dual-programmable 32-bit timers and Watch Dog Timer. Topics include timer registers (TMRx, TCRx and TRRx), timer operation, timer interrupts, and timer register values at initialization. Each timer is programmed by the timer registers. These registers are mapped into Intel XScale® processor Coprocessor 6, registers 0 to 8. They may be accessed/manipulated with the MCR, MRC, STC, and LDC instructions.
PAGE 628
Intel® 413808 and 413812—Timers 11.1 Timer Operation 11.1.1 Basic Programmable Timer Operation This section summarizes the programmable timer and Watch Dog Timer operation and describes load/store access latency for the timer registers. Each timer has a programmable enable bit in its control register (TMRx.enable) to start and stop counting. This allows the programmer to prevent user mode tasks from enabling or disabling the timer.
PAGE 629
Timers—Intel® 413808 and 413812 11.1.2 Note: Watch Dog Timer Operation The Watch Dog Timer (WDT) is a ®32-bit down counter that can be used to reset the Internal Bus and the Intel XScale processor or generate an interrupt when software gets stuck in an infinite loop. Refer to Section 426, “Watch Dog Timer Setup Register — WDTSR” on page 639 for setting up the Watchdog timer.
PAGE 630
Intel® 413808 and 413812—Timers 11.1.3 Load/Store Access Latency for Timer Registers As with all other load accesses from internal memory-mapped registers, a load instruction that accesses a timer register has a latency of one internal processor cycle. With one exception, a store access to a timer register completes and all state changes take effect before the next instruction begins execution. The exception to this is when disabling a timer.
PAGE 631
Timers—Intel® 413808 and 413812 11.2 Timer Interrupts Each timer is the source for one interrupt. When a timer detects a zero count in its TCRx, the timer generates an internal level-detected Timer Interrupt signal (TINTx) to the interrupt controller, and the interrupt source (INTSRC[1:0]) bit is set in the interrupt controller. Each timer interrupt can be selectively masked in the Interrupt Control (INTCTL[1:0]) registers.
PAGE 632
Intel® 413808 and 413812—Timers 11.3 Timer State Diagram Figure 72 shows the common states of the Timer Unit. For uncommon conditions see Section 11.5, “Uncommon TCRX and TRRX Conditions” on page 640. Figure 72. Timer Unit State Diagram Hardware / Software Reset TMRx.enable = 0 TMRx.reload = 0 TMRx.pri = 0 TMRx.csel1:0 = 0 IPND.tip = 0 SW Write (TMRx.enable = 0) IDLE Bus Clock or SW Read SW Write (TMRx.enable = 1 TMRx.enable = 1 TMRx.reload = user value TMRx.pri = user value TMRx.
PAGE 633
Timers—Intel® 413808 and 413812 11.4 Timer Registers As shown in Table 418, each timer has three co-processor registers: • Timer Mode Register — programs the specific mode of operation or indicates the current programmed status of the timer. This register is described in Section 11.4.2, “Timer Mode Registers – TMR0:1” on page 634. • Timer Count Register — contains the timer’s current count. See Section 11.4.3, “Timer Count Register – TCR0:1” on page 637.
PAGE 634
Intel® 413808 and 413812—Timers 11.4.2 Timer Mode Registers – TMR0:1 The Timer Mode Register (TMRx) lets the user program the mode of operation and determine the current status of the timer. TMRx bits are described in the subsections following Table 420 and are summarized in Table 416. Table 420.
PAGE 635
Timers—Intel® 413808 and 413812 11.4.2.1 11.4.2.2 Bit 0 — Terminal Count Status Bit (TMRx.tc) The TMRx.tc bit is set when the Timer Count Register (TCRx) decrements to 0 and bit 2 (TMRx.reload) is not set for a timer. The TMRx.tc bit allows applications to monitor timer status through software instead of interrupts. TMRx.tc remains set until software accesses (reads or writes) TMRx. The access clears TMRx.tc. The timer ignores any value specified for TMRx.tc in a write request.
PAGE 636
Intel® 413808 and 413812—Timers 11.4.2.4 Bit 3 — Timer Register Privileged Read/Write Control (TMRx.pri) The TMRx.pri bit enables or disables user mode writes to the timer registers (TMRx, TCRx, TRRx). Privileged mode writes are allowed regardless of this bit’s condition. Software can read these registers from either mode. Note that TMR1.pri also controls write access to the “Watch Dog Timer Control Register — WDTCR” on page 639 and the “Watch Dog Timer Setup Register — WDTSR” on page 639. When: TMRx.
PAGE 637
Timers—Intel® 413808 and 413812 11.4.3 Timer Count Register – TCR0:1 The Timer Count Register (TCRx) is a 32-bit register that contains the timer’s current count. The register value decrements with each timer clock tick. When this register value decrements to zero (terminal count), a timer interrupt is generated. When TMRx.reload is not set for the timer, the status bit in the timer mode register (TMRx.tc) is set and remains set until the TMRx register is accessed.
PAGE 638
Intel® 413808 and 413812—Timers 11.4.5 Timer Interrupt Status Register – TISR The Timer Interrupt Status Register (TISR; Table 424) is a three-bit register that contains the timer’s pending interrupt status and the Watchdog pending interrupt status (when enabled). The setting of these status bits represents the assertion of a “level-sensitive” interrupt request to the Interrupt Controller Unit.
PAGE 639
Timers—Intel® 413808 and 413812 11.4.6 Watch Dog Timer Control Register – WDTCR The Watch Dog Timer Control Register (WDTCR) is a 32-bit register that software can use to enable the WDT or read the current WDT count value. The register value decrements with each internal bus clock tick. When this register value decrements to zero (terminal count), an Internal Bus Reset or an interrupt is generated. Refer to Section 426, “Watch Dog Timer Setup Register — WDTSR” on page 639.
PAGE 640
Intel® 413808 and 413812—Timers 11.5 Uncommon TCRx and TRRx Conditions Table 416 summarizes the most common settings for programming the timer registers. Under certain conditions, however, it may be useful to set the Timer Count Register or the Timer Reload Register to zero before enabling the timer. Table 427 details the conditions and results when these conditions are set. Table 427. Uncommon TMRx Control Bit Settings TRRx TCRx X 0 0 0 Bit 2 Bit 1 (TMRx.reloa d) (TMRx.
PAGE 641
SMBus Interface Unit—Intel® 413808 and 413812 12.0 SMBus Interface Unit This chapter describes the SMBus (System Management Bus) interface unit, including the operation modes and setup. Throughout this manual, this peripheral is referred to as the SMBus unit. 12.1 12.2 Overview The SMBus Interface Units allows the Intel® 413808 and 413812 I/O Controllers in TPER Mode (4138xx) to serve as a slave device residing on the SMBus. The SMBus is a two-pin interface.
PAGE 642
Intel® 413808 and 413812—SMBus Interface Unit 12.3 System Management Bus Interface This interface has no configuration registers associated with it. The SMBus address is set upon P_RST# by sampling the Peripheral Bus Interface Reset Strap inputs A[16:13]. When the pins are sampled, the resulting 4138xx address is stored in the Reset Strap Status Register and assigned as follows: Bit Value 7 6 5 4 3 2 1 1 1 A[16] 0 A[15] A[14] A[13] The SMBus controller has access to all internal registers.
PAGE 643
SMBus Interface Unit—Intel® 413808 and 413812 12.3.1 SMBus Controller 12.3.1.1 SMBus Commands The 4138xx SMBus slave port interfaces to the configuration spaces of each ATU function, and also interfaces to the memory-mapped registers. This gives SM (server management) visibility into configuration space registers in the 4138xx ATUs 4138xx.
PAGE 644
Intel® 413808 and 413812—SMBus Interface Unit 12.3.1.2 Initialization Sequence All Configuration and memory reads and writes are accomplished through an SMBus write(s) and later followed by an SMBus read (for a read command).
PAGE 645
SMBus Interface Unit—Intel® 413808 and 413812 12.3.2 SMBus Signaling 12.3.2.1 Overview 12.3.2.2 The SMBus interface includes a pair of signals: SMBCLK (clock) and SMBDAT (serial data). SMBCLK provides the timing mechanism for data transfers. The SMBus master always drives SMBCLK. The 4138xx may optionally extend SMBCLK low time by driving it low to meet setup timings on the SMBus. An initiator starts a transfer over the SMBus when it is free. Details of how initiators arbitrate are not described here.
PAGE 646
Intel® 413808 and 413812—SMBus Interface Unit 12.3.2.2.2 Stop Phase A stop condition is generated when SMBus is busy to indicate that its state is changing to idle. The Stop condition occurs when SMBDAT transitions from Low to High while SMBCLK remains High. Figure 75. Stop (P) Signaling SMBCLK SMBDAT B6278-01 A stop bit can occur at any point in a data stream. It is not insured to occur after an ACK from a target (as later waveforms show).
PAGE 647
SMBus Interface Unit—Intel® 413808 and 413812 12.3.3 Architecture The 4138xx SMBus register interface consists of a set of registers that are only accessible from the SMBus interface only and are shown in Table 430 and Table 431. These registers are used to issue commands for reading and writing configuration registers and memory locations on 4138xx Table 430 shows that register format for accessing configuration space.
PAGE 648
Intel® 413808 and 413812—SMBus Interface Unit clock until such time that the data is delivered. Note that per the SMBus specification, this cannot be longer than 25 ms. To set up an internal access, the command register write is followed by four ADDR byte writes. Depending on the type of access, these four bytes indicate either the Bus number, Device, Function, Extended Register Offset, and Register Offset, or the Memory-mapped region selected and the address within the region.
PAGE 649
SMBus Interface Unit—Intel® 413808 and 413812 12.3.3.1 Data Transfer Examples 12.3.3.2 Configuration and Memory Reads For Figure 78 through Figure 85, the following terminology is used: S Start Bit Sr Start Repeat Bit W Write Command R Read Command A Acknowledge N Retry / not Acknowledge P Stop Bit Clear boxes indicate phases of the cycle driven by the initiator, and shaded boxes indicate phases of the cycle driven by the target. 4138xx supports only read dword to internal register space.
PAGE 650
Intel® 413808 and 413812—SMBus Interface Unit Figure 79. DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Enabled) Figure 80. DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled) Figure 81. DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled) Figure 82.
PAGE 651
SMBus Interface Unit—Intel® 413808 and 413812 Figure 83. DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Disabled) Figure 84. DWORD Memory Read Protocol (SMBus Word Write/(Word, Byte) Read, PEC Enabled) Figure 85.
PAGE 652
Intel® 413808 and 413812—SMBus Interface Unit 12.3.3.3 Configuration and Memory Writes Configuration and memory writes are accomplished through a series of SMBus writes. As with reads, a write sequence is first used to initialize the Bus Number, Device, Function, and Register Number for the configuration access and the destination memory, address offset for the memory write.
PAGE 653
SMBus Interface Unit—Intel® 413808 and 413812 Figure 88.
PAGE 654
Intel® 413808 and 413812—SMBus Interface Unit 12.3.4 Error Handling 12.3.5 SMBus Interface Reset The SMBus slave interface handles two types of errors: internal address error and PEC. Internal address errors can occur, for example, when the SMBus request on the 4138xx internal bus fails due to an address parity error. This error manifests itself as a Not-Acknowledge (NACK) for the read or write command (End bit is set).
PAGE 655
SMBus Interface Unit—Intel® 413808 and 413812 12.4 Register Definitions This section provides a summary descriptions of all the SMbus registers. The SMBus Interface Unit has eight registers which are accessible from the SMBus interface only. Firmware cannot access these registers on 4138xx. Table 433.
PAGE 656
Intel® 413808 and 413812—SMBus Interface Unit 12.4.2 SMBus Controller Byte Count Register — SM_BC The SM_BC register indicates the number of bytes following the command field when performing a write or when setting up for a read. The byte count is also used when returning the data to indicate the following bytes including the status byte which is returned prior to the data. Note that the byte count is only transmitted for block type accesses on SMBus.
PAGE 657
SMBus Interface Unit—Intel® 413808 and 413812 12.4.5 SMBus Controller ADDR1 Register Number — SM_ADDR1 This register should be programmed with the upper address bits (bits [11:8]) of the Register Number of the desired configuration register for 4-KByte configuration space. 4138xx ignores bit [7:4] of this register. The Status Register should be checked to make sure that there is not a command currently in progress, before writing to this register.
PAGE 658
Intel® 413808 and 413812—SMBus Interface Unit 12.4.7 SMBus Controller Data Register — SM_DATA This register is used to read or write data to the desired Configuration Register. At the completion of a Read command, this register contains the data from the selected configuration register. For reads the data register always returns 32 bits and is always aligned on a DWORD boundary. Before issuing a write command this register should be written with the desired write data.
PAGE 659
UARTs—Intel® 413808 and 413812 13.0 UARTs Note: UART0 is owned by the Transport Core. See the System/Software Architecture Specification for details on how to change this. This chapter describes the Universal Asynchronous Receiver/Transmitter (UART) serial ports. The Intel® 413808 and 413812 I/O Controllers in TPER Mode (4138xx) UARTs are controlled via programmed I/O through memory-mapped registers. 13.1 Overview Each asynchronous serial port supports all the functions of 16550 UART.
PAGE 660
Intel® 413808 and 413812—UARTs The UART hardware is responsible for executing serial protocol communication and for providing the programming interface.
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UARTs—Intel® 413808 and 413812 13.2 Signal Descriptions The name and description of external signals connected to a UART module are shown in Table 442. Table 442. UART Signal Descriptions Name* Type Ux_RXD Input Ux_TXD Output Ux_CTS# Input Ux_RTS# Output Note: Description SERIAL INPUT: Serial data input from device pin to the receive shift register. SERIAL OUTPUT: Composite serial data output to the communications link-peripheral, modem, or data set.
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Intel® 413808 and 413812—UARTs 13.3 Theory of Operation The format of a UART data frame is shown in Figure 89. Figure 89. Example UART Data Frame Start Bit Data< Data< Data< Data< Data< Data< Data< Data< 0> 1> 2> 3> 4> 5> 6> 7> TXD or RXD pin LSB Parity Bit Stop Bit 1 Stop Bit 2 MSB Shaded bits are optional and can be programmed by user. —> Each data frame is between 7 bits and 12 bits long, depending on the size of data programmed and when parity and stop bits are enabled.
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UARTs—Intel® 413808 and 413812 13.3.1 FIFO Interrupt Mode Operation 13.3.1.1 Receiver Interrupt 13.3.1.2 When the Receive FIFO and receiver interrupts are enabled (FCR[0]=1 and IER[0]=1), receiver interrupts occur as follows: • The Receive Data Available Interrupt is asserted when the FIFO has reached its programmed trigger level. The interrupt is cleared when the FIFO drops below the programmed trigger level.
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Intel® 413808 and 413812—UARTs 13.3.2 Removing Trailing Bytes In Interrupt Mode 13.3.2.1 Character Time-out Interrupt When the number of entries in the Receive FIFO is less than its trigger level, and no additional data is received, the remaining bytes are called trailing bytes.
PAGE 665
UARTs—Intel® 413808 and 413812 13.3.4 Autoflow Control 13.3.4.1 RTS Autoflow 13.3.4.2 Autoflow Control uses the Clear-to-Send (CTS#) and Request-to-Send (RTS#) signals to automatically control the flow of data between the UART and external modem. When autoflow is enabled, the remote device is not allowed to send data unless the UART asserts nRTS low. When the UART deasserts RTS# while the remote device is sending data, the remote device is allowed to send one additional byte after RTS# is deasserted.
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Intel® 413808 and 413812—UARTs 13.3.5 Auto-Baud-Rate Detection Each UART supports auto-baud-rate detection. When enabled, UART counts the number of 33.334 MHz clock cycles within the start-bit pulse. This number is then written into the Auto-Baud-Count register (ACR) and used to calculate the baud rate. When ACR is written, an Auto-Baud-Lock Interrupt is generated (when enabled), and the UART automatically programs the Divisor Latch registers with the appropriate baud rate.
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UARTs—Intel® 413808 and 413812 13.3.6 Manual Baud Rate Selection Each UART contains a programmable Baud Rate Generator that is capable 16 of taking the fixed input clock of 33.334 MHz and dividing it by any divisor from 1 to (2 –1). The baud-rate generator output frequency is 16 times the baud rate. Two 8-bit registers store the divisor in a 16-bit binary format. These Divisor Registers must be loaded during initialization to ensure proper operation.
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Intel® 413808 and 413812—UARTs 13.4 Register Descriptions There are 15 registers in each UART. The registers are all 32 bit registers, but only lower 8 bits have valid data. The 12 UART registers share eight address locations in the MMR address space. Table 444 shows the registers and their addresses as offsets of a base address. The base address for each UART is 32 bits and is internal bus address offset 2300H for UART 0, and 2340H for UART 1.
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UARTs—Intel® 413808 and 413812 Table 446. UART Register MMR Addresses UART Register Addresses DLAB Bit Value Name Register Accessed 0 0 0 X X X X X X X 1 1 X X X 0 0 0 X X X X X X X 1 1 X X X U0RBR U0THR U0IER U0IIR U0FCR U0LCR U0MCR U0LSR U0MSR U0SPR U0DLL U0DLH U0FOR U0ABR U0ACR U1RBR U1THR U1IER U1IIR U1FCR U1LCR U1MCR U1LSR U1MSR U1SPR U1DLL U1DLH U1FOR U1ABR U1ACR UART 0 Receive BUFFER (read only) UART 0 Transmit BUFFER (write only) UART 0 Interrupt Enable (R/W) UART 0 Interrupt I.D.
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Intel® 413808 and 413812—UARTs 13.4.1 UART x Receive Buffer Register In non-FIFO mode, this register holds the character(s) received by the UART Receive Shift register. When it receives fewer than eight bits, the bits are right-justified and the leading bits are zeroed. Reading the register empties the register and resets the data ready (DR) bit in the Line Status register to 0. Other (error) bits in the Line Status register are not cleared.
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UARTs—Intel® 413808 and 413812 13.4.3 Note: UART x Interrupt Enable Register This register enables six types of interrupts which set a value in the Interrupt Identification register. Each of the six interrupt types can be disabled by clearing the appropriate bit of the IER register. Similarly, by setting the appropriate bits, selected interrupts can be enabled. This register also has the control bits of the unit enable and NRZ coding enable.
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Intel® 413808 and 413812—UARTs 13.4.4 UART x Interrupt Identification Register The IIR register is read to determine the type and source of UART interrupts. To be 16550 compatible, the lower 4 bits (0-3) of the IIR register are priority encoded as shown in Table 451, “Interrupt Identification Register Decode” on page 673. When two or more interrupts represented by bits (0-3) occur, only the interrupt with the highest priority is displayed. The upper 4 bits, (4-7) are not priority encoded.
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UARTs—Intel® 413808 and 413812 Table 451. Interrupt Identification Register Decode Interrupt ID bits 3 2 1 0 IP# IID[11] IID[10] TOD IID[01] IID[00] 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 Priority Highest Type No Interrupt is pending. Receiver Line Status Overrun Error, Parity Error, Framing Error, Break Interrupt. Reading the Line Status Register. Non-FIFO mode: Receive Buffer is full. Non-FIFO mode: Reading the Receiver Buffer Register.
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Intel® 413808 and 413812—UARTs 13.4.5 UART x FIFO Control Register FCR is a write only register that is located at the same address as the IIR (IIR is a read only register). FCR enables/disables the transmitter/receiver FIFOs, clears the transmitter/receiver FIFOs, and sets the receiver FIFO trigger level. Table 452.
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UARTs—Intel® 413808 and 413812 Table 452.
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Intel® 413808 and 413812—UARTs 13.4.6 UART x Line Control Register In the Line Control Register, the system programmer specifies the format of the asynchronous data communications exchange. The serial data format consists of a start bit (logic 0), five to eight data bits, an optional parity bit, and one or two stop bits (logic 1). The LCR has bits for accessing the Divisor Latch registers and causing a Break condition. The programmer can also read the contents of the Line Control Register.
PAGE 677
UARTs—Intel® 413808 and 413812 Table 453.
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Intel® 413808 and 413812—UARTs 13.4.7 UART x Modem Control Register This register controls the interface with the modem or data set (or a peripheral device emulating a modem). The contents of the Modem Control register are described below: Table 454.
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UARTs—Intel® 413808 and 413812 Table 454.
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Intel® 413808 and 413812—UARTs 13.4.8 UART x Line Status Register This register provides status information to the processor concerning the data transfers. Bits 5 and 6 show information about the transmitter section. The remainder of the bits contain information about the receiver. In non-FIFO mode, three of the LSR register bits, parity error, framing error, and break interrupt, show the error status of the character that has just been received.
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UARTs—Intel® 413808 and 413812 Table 455.
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Intel® 413808 and 413812—UARTs Table 455.
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UARTs—Intel® 413808 and 413812 Table 456. UART x Modem Status Register Note: This register provides the current state of the control lines from the modem or data set (or a peripheral device emulating a modem). In addition to this current state information, the Modem Status register also provides change information. The change bit is set to a logic 1 when the control input from the Modem changes state. The change bit is reset to a logic 0 when the processor reads the Modem Status register.
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Intel® 413808 and 413812—UARTs 13.4.9 UART x Scratchpad Register This read/write register has no effect on the UART. It is intended as a scratchpad register for use by programmers. Table 458.
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UARTs—Intel® 413808 and 413812 13.4.10 Divisor Latch Registers The description of use for the Divisor Latch Registers are provided in Section 13.3.5, Auto-Baud-Rate Detection and Section 13.3.6, Manual Baud Rate Selection. Refer to those sections for details on how to program these registers. Bit DLAB in the LCR register must be set high before the Divisor Latch registers can be accessed. A Divisor value of 0 in the Divisor Latch Register is not allowed. A value of 0 has the affect of disabling the UART.
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Intel® 413808 and 413812—UARTs 13.4.11 UART x FIFO Occupancy Register This register shows the number of bytes currently remaining the Receive FIFO. It can be used by the processor to determine the number of trailing bytes to remove from the receive FIFO when the Character Time-out Interrupt is detected. Refer to Section 13.3.2, “Removing Trailing Bytes In Interrupt Mode” on page 664.
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UARTs—Intel® 413808 and 413812 13.4.12 UART x Auto-Baud Control Register This read/write register has no effect on the UART. It is intended as a scratchpad register for use by programmers. Table 462.
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Intel® 413808 and 413812—UARTs 13.4.13 UART x Auto-Baud Count Register The Auto-Baud Count register stores the number of 33.334 MHZ clock cycles within a start bit pulse. This value is then used by the processor or auto-baud circuitry within the UART to calculate the baud rate. When Auto-Baud mode and Auto-Baud Interrupts are enabled, the UART interrupt the processor with the Auto-Baud Lock Interrupt after it has written the count value into the ACR.
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I2C Bus Interface Units—Intel® 413808 and 413812 2 14.0 I C Bus Interface Units Note: I2C0 is owned by the Ttransport Core. See the System/Software Architecture Specification for details on how to change this. This chapter describes the three I C (Inter-Integrated Circuit) bus interface units, including the operation modes and setup. Throughout this manual, these peripherals are referred to as the I C units. 2 2 14.
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Intel® 413808 and 413812—I2C Bus Interface Units 14.2 Theory of Operation The I C bus defines a serial protocol for passing information between agents on the I C bus, using only a two pin interface. The interface consists of a Serial Data/Address (SDA) line and a Serial Clock Line (SCL). Each device on the I C bus is recognized by a unique 7-bit address and can operate as a transmitter or as a receiver. In addition to transmitter and receiver, the I C bus uses the concept of master and slave.
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I2C Bus Interface Units—Intel® 413808 and 413812 The I C bus allows for a multi-master system, which means more than one device can initiate data transfers at the same time. To support this feature, the I C bus arbitration relies on the wired-AND connection of all I C interfaces to the I C bus. Two masters can drive the bus simultaneously provided they are driving identical data. The first master to drive SDA high while another master drives SDA low loses the arbitration.
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Intel® 413808 and 413812—I2C Bus Interface Units 14.2.1 Operational Blocks The I C Bus Interface Unit is a slave peripheral device that is connected to the internal bus. The 4138xx interrupt mechanism can be used for notifying the 4138xx that there is activity on the I C bus. Polling can be also be used instead of interrupts, although it would be very cumbersome. Figure 92 shows a block diagram of the I C Bus Interface Unit and its interface to the internal bus.
PAGE 693
I2C Bus Interface Units—Intel® 413808 and 413812 The I C interrupts are signalled through a single pin which provides a level sensitive interrupt to the 4138xx interrupt control unit. The I C Bus Interface Unit can cause and interrupt when a buffer is full, buffer empty, slave address detected, arbitration lost, or bus error condition occurs. All interrupt conditions must be cleared explicitly by software. See Section 14.8.2, “I2C Status Register x — ISRx” on page 717 for details.
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Intel® 413808 and 413812—I2C Bus Interface Units 14.2.2 I2C Bus Interface Modes The I C Bus Interface Unit can be in different modes of operation to accomplish a transfer. Table 465 summarizes the different modes. 2 Table 465. Modes of Operation Mode Master — Transmit Master — Receive Slave — Transmit Slave — Receive (default) Definition • • • • • • • • • • • • • • • • • • I2C Bus Interface Unit acts as a master. Used for a write operation. I2C Bus Interface Unit sends the data.
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I2C Bus Interface Units—Intel® 413808 and 413812 14.2.3 Start and Stop Bus States The I C bus defines a transaction START and a transaction STOP bus state that are used at the beginning and end of the transfer of one to an unlimited number of bytes on the bus.
PAGE 696
Intel® 413808 and 413812—I2C Bus Interface Units 14.2.3.1 START Condition The START condition (bits 1:0 of the ICR set to 012) initiates a master transaction or repeated START. Software must load the target slave address and the R/W# bit in the IDBR (see Section 14.8.4, “I2C Data Buffer Register x — IDBRx” on page 720) before setting the START ICR bit. The START and the IDBR contents are transmitted on the I C bus when the ICR Transfer Byte bit is set.
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I2C Bus Interface Units—Intel® 413808 and 413812 14.3 2 I C Bus Operation The I C Bus Interface Unit transfers in 1 byte increments. A data transfer on the I C bus always follows the sequence: 1. START. 2. 7-bit Slave Address. 3. R/W# Bit. 4. Acknowledge Pulse. 5. 8 Bits of Data. 6. Ack/Nack Pulse. 7. Repeat of Step 5 and 6 for Required Number of Bytes. 8. Repeated START (Repeat Step 1) or STOP. 9. Serial Clock Line (SCL) Generation.
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Intel® 413808 and 413812—I2C Bus Interface Units 14.3.1.1 Addressing a Slave Device As a master device, the I C unit must compose and send the first byte of a transaction. This byte consists of the slave address for the intended device and a R/W# bit for transaction definition. The slave address and the R/W# bit are written to the IDBR (see Figure 95). 2 Figure 95.
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I2C Bus Interface Units—Intel® 413808 and 413812 14.3.2 I2C Acknowledge Every I C byte transfer must be accompanied by an acknowledge pulse, which is always generated by the receiver (master or slave). The transmitter must release the SDA line for the receiver to transmit the acknowledge pulse (see Figure 96). In master-transmit mode, when the target slave receiver device cannot generate the acknowledge pulse, the SDA line remains high.
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Intel® 413808 and 413812—I2C Bus Interface Units 14.3.3 Arbitration Arbitration on the I C bus is required due to the multi-master capabilities of the I C bus. Arbitration is used when two or more masters simultaneously generate a START condition within the minimum I C hold time of the START condition. Arbitration can continue for a long period. When the address bit and the R/W# are the same, the arbitration moves to the data.
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I2C Bus Interface Units—Intel® 413808 and 413812 14.3.3.2 SDA Arbitration Arbitration on the SDA line can continue for a long period, starting with address and R/W# bits and continuing with data bits. Figure 98 shows the arbitration procedure for two masters (more than two may be involved depending on how many masters are connected to the bus). When the address and R/W# are the same, arbitration moves to the data.
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Intel® 413808 and 413812—I2C Bus Interface Units 14.3.4 Master Operations When software initiates a read or write on the I C bus, the I C unit transitions from the default slave-receive mode to master-transmit mode. The start pulse is sent followed by the 7-bit slave address and the R/W# bit.
PAGE 703
I2C Bus Interface Units—Intel® 413808 and 413812 Table 467.
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Intel® 413808 and 413812—I2C Bus Interface Units When the 4138xx needs to read data, the I C unit transitions from slave-receive mode to master-transmit mode to transmit the start address and immediately following the ACK pulse transitions to master-receive mode to wait for the reception of the read data from the slave device (see Figure 99).
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I2C Bus Interface Units—Intel® 413808 and 413812 14.3.5 Slave Operations Table 468 describes the I C Bus Interface Unit’s responsibilities as a slave device. 2 Table 468.
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Intel® 413808 and 413812—I2C Bus Interface Units Figure 102 through Figure 104 are examples of I C transactions. These show the relationships between master and slave devices. 2 Figure 102. Master-Transmitter Write to Slave-Receiver R/W# ACK 0 Slave Address START First Byte Data Byte Write ACK Data Byte ACK STOP N Bytes + ACK Master to Slave Slave to Master B6292-01 Figure 103.
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I2C Bus Interface Units—Intel® 413808 and 413812 14.3.6 General Call Address The I C unit supports both sending and receiving general call address transfers on the I C bus. When sending a general call message from the I C unit, software must set the General Call Disable bit in the ICR to keep the I C unit from responding as a slave. Failure to set this bit causes the I C Bus to enter an indeterminate state. A general call address is defined as a transaction with a slave address of 00H.
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Intel® 413808 and 413812—I2C Bus Interface Units 14.4 Slave Mode Programming Examples 14.4.1 Initialize Unit 14.4.2 Write 1 Byte as a Slave 14.4.3 Read 2 Bytes as a Slave 1. Write ISAR: Set slave address 2. Write ICR: Enable all interrupts, set Unit Enable 1. Wait for Slave Address Detected interrupt. Read ISR: Slave Address Detected (set), Unit Busy (set), R/W# bit (1), Ack/Nack (Clear - Ack) 2. Write IDBR: Load data byte to transfer 3. Write ICR: Set Transfer Byte bit 4.
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I2C Bus Interface Units—Intel® 413808 and 413812 14.5 Master Programming Examples 14.5.1 Initialize Unit 14.5.2 Write 1 Byte as a Master Note: 14.5.3 1. Write ISAR: Set slave address 2. Write ICR: Enable all interrupts (except Arb Loss), set SCL Enable, set Unit Enable 1. Write IDBR: Target slave address and R/W# bit (0 for write) 2. Write ICR: Set START bit, Clear STOP bit, Set Transfer Byte bit to initiate the access 3. Wait for IDBR Transmit Empty interrupt.
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Intel® 413808 and 413812—I2C Bus Interface Units 14.5.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master 1. Write IDBR: Target slave address and R/W# bit (0 for write) 2. Write ICR: Set START bit, Clear STOP bit, Set Transfer Byte bit to initiate the access 3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives: Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (clear) Clear IDBR Transmit Empty bit to clear the interrupt. 4.
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I2C Bus Interface Units—Intel® 413808 and 413812 14.5.5 Note: Read 2 Bytes as a Master — Send STOP Using the Abort 1. Write IDBR: Target slave address and R/W# bit (1 for read) 2. Write ICR: Set START bit, Clear STOP bit, Disable Arb loss interrupt, Set Transfer Byte bit to initiate the access 3. Wait for IDBR Transmit Empty interrupt. When interrupt comes. Read status register: IDBR Transmit Empty (set), Unit Busy (set), R/W# bit (set) Clear IDBR Transmit Empty bit to clear the interrupt. 4.
PAGE 712
Intel® 413808 and 413812—I2C Bus Interface Units 14.6 Glitch Suppression Logic The I C Bus Interface Unit has built-in glitch suppression logic. Glitches are suppressed according to: 2 * I C clock period. For example, with the 33 MHz (30. ns period) I C clock glitches of 60ns or less are suppressed. This is within the 50 ns glitch suppression specified.
PAGE 713
I2C Bus Interface Units—Intel® 413808 and 413812 14.7 Reset Conditions The I C unit is reset with internal bus reset. Software is responsible for ensuring the I C unit is not busy (ISR[3]) before asserting reset. Software is also responsible for ensuring the I C bus is idle when the unit is enabled after reset. When directed to reset, the I C unit returns to its default reset condition with the exception of the ISAR. ISAR is not affected by a reset.
PAGE 714
Intel® 413808 and 413812—I2C Bus Interface Units 14.8 Register Definitions The following registers are associated with the I C Bus Interface Units. Each I C Bus Interface Unit has five memory-mapped control registers for independent operation. In register titles, x is 0 or 1 for unit 0 or 1, respectively. They are all located within the peripheral memory- mapped address space of the 4138xx. 2 2 Table 470. I2C Register Summary Section, Register Name, Acronym, Page Section 14.8.
PAGE 715
I2C Bus Interface Units—Intel® 413808 and 413812 14.8.1 I2C Control Register x — ICRx The 4138xx uses the bits in the I C Control Register (ICRx) to control the I C unit. 2 2 Table 471.
PAGE 716
Intel® 413808 and 413812—I2C Bus Interface Units Table 471.
PAGE 717
I2C Bus Interface Units—Intel® 413808 and 413812 14.8.2 I2C Status Register x — ISRx I C interrupts are signalled to the 4138xx interrupt controller by the I C Interrupt Status Register (ISRx). Software uses the ISR bits to check the status of the I C unit and bus. ISRx bits (bits 9-5) are updated after the Ack/Nack bit has completed on the I C bus. The ISRx is also used to clear interrupts signalled from the I C Bus Interface Unit.
PAGE 718
Intel® 413808 and 413812—I2C Bus Interface Units Table 472.
PAGE 719
I2C Bus Interface Units—Intel® 413808 and 413812 14.8.3 I2C Slave Address Register x — ISARx The I C Slave Address Register (ISARx) (see Table 473) defines the I C unit 7-bit slave address to which the 4138xx responds when in slave-receive mode. This register is written by the 4138xx before enabling I C operations. The register is fully programmable (no address is assigned to the I C unit) so it can be set to a value other than those of hard-wired I C slave peripherals that might exist in the system.
PAGE 720
Intel® 413808 and 413812—I2C Bus Interface Units 14.8.4 I2C Data Buffer Register x — IDBRx The I C Data Buffer Register (IDBRx) is used by the 4138xx to transmit and receive data from the I C bus. The accesses the IDBRx by the 4138xx on one side and by the I C shift register on the other. Data coming into the I C Bus Interface Unit is received into the IDBRx after a full byte has been received and acknowledged.
PAGE 721
I2C Bus Interface Units—Intel® 413808 and 413812 14.8.5 I2C Bus Monitor Register x — IBMRx The I C Bus Monitor Register (IBMRx) tracks the status of the SCL and SDA pins. The values of these pins are recorded in this read-only register so that software may determine if the I C bus is hung and the I C unit must be reset. 2 2 2 Table 475.
PAGE 722
Intel® 413808 and 413812—I2C Bus Interface Units 14.8.6 I2C Manual Bus Control Register x — IMBCRx The I C Manual Bus Control Register (IMBCRx) can be used to manually release or pull down the SCL and SDA pins. The values of these pins are controlled by the IMBCRx bits 2:1 when bit 0 of the IMBCRx is set. When software determines that the I C bus is hung using the “I2C Bus Monitor Register x — IBMRx” on page 721, this register may be used to force the I C bus out of the hung state.
PAGE 723
General Purpose I/O Unit—Intel® 413808 and 413812 15.0 General Purpose I/O Unit Note: For TPER mode the register interface defined here is used. For 4138xx non-TPER mode, see the SAS/SATA Command Summary for API to control the GPIO units. Some limitations apply when controlling via the API.
PAGE 724
Intel® 413808 and 413812—General Purpose I/O Unit 15.2 Register Definitions All GPIO are visible as 4138xx memory mapped registers and can be accessed through the internal memory bus. Each is a 32-bit register and is memory-mapped in the Intel XScale processor memory space. The programmer interface to the General Purpose I/O is through memory-mapped control registers. Table 477 describes these registers. ® k‘ Table 477.
PAGE 725
General Purpose I/O Unit—Intel® 413808 and 413812 15.2.1 GPIO Output Enable Register — GPOE The GPIO Output Enable Register, on a per pin basis, enables the output value contained in the GPIO Output Data Register, onto the appropriate pin. The GPIO Output Enable Register is initialized to FFFFH such that all of GPIO[15:0] are inputs. In order to enable a particular GPIO pin to operate as an output following the deassertion of P_RST#, the user needs to write a 0 into the appropriate GPOE bit. Table 478.
PAGE 726
Intel® 413808 and 413812—General Purpose I/O Unit 15.2.2 GPIO Input Data Register — GPID The GPIO Input Data Register reflects the state of the appropriate GPIO bus pins following the deassertion of P_RST#. Table 479.
PAGE 727
General Purpose I/O Unit—Intel® 413808 and 413812 Table 479.
PAGE 728
Intel® 413808 and 413812—General Purpose I/O Unit 15.2.3 GPIO Output Data Register — GPOD The GPIO Output Data Register is driven on a per bit basis on the appropriate GPIO bus pins following the deassertion of P_RST# when the corresponding bit in the GPOE register is cleared. Table 480.
PAGE 729
PMON Unit—Intel® 413808 and 413812 16.0 PMON Unit 16.1 PMON Counters 16.2 Overview The Performance Monitoring (PMON) counters enable performance monitoring and gathering statistics of internal hardware events in real-time. This implementation provides users with direct event counting and timing for performance monitoring and system debugging purposes. It provides enough visibility into the internal architecture to perform utilization studies, workload characterization, and application tuning.
PAGE 730
Intel® 413808 and 413812—PMON Unit 16.2.1 Clock Counter Control When a counter is sampled, the current value of the counter is latched into the corresponding data register. The command, event, status, and data registers are accessible via memory mapped registers in order to facilitate high-speed sampling. Figure 107.
PAGE 731
PMON Unit—Intel® 413808 and 413812 16.3 Definitions • Duration Count - The counter is incremented for each clock for which the event signal is asserted logic high. • Occurrence Count - The counter is incremented each time a rising edge of the event signal is detected. • Preconditioning - Altering a signal that represents an event before it is presented to be counted by the PMON unit. This includes clock crossing logic. Two optional external pins allow for external visibility and control of the counters.
PAGE 732
Intel® 413808 and 413812—PMON Unit 16.4 Data Collection 16.4.1 Time Based Sampling The following sections provide some insight into the intended use of the PMON counters at a very low level. The examples and accompanying explanation should prove especially valuable in the creation of test cases for both hardware and software. The hardware face to the PMON counters is not intended to be any wider than 32 bits. This means that all registers are accessed one at a time.
PAGE 733
PMON Unit—Intel® 413808 and 413812 Example 7 has been simplified by using 12 clocks as the sampling period. In a real system the sampling would more likely be something like 1 ms. There is a certain amount of overhead associated with writing and reading to any PMON registers. The more frequent the interaction between the PMON counters and any software, the larger the margin of error that is injected into the final results.
PAGE 734
Intel® 413808 and 413812—PMON Unit 16.4.2 Hardware Event Based Control Hardware event based control allows a hardware event to control when another command is executed. An example of this is controlling when a sample (snapshot) is taken of the active counter(s). This is required to facilitate, among other things, hardware data queue analysis. No command is executed until the command trigger mux detects the event in the command trigger field of the command register.
PAGE 735
PMON Unit—Intel® 413808 and 413812 However, execution of this command is conditional upon a cache hit occurring (Event B in Example 8). Thus, the cache hit command becomes the “Command Trigger” that must occur before the memory read events would no longer be counted. Example 8. How many Event A’s happen before the first Event B is detected This example demonstrates how to measure the number of times event A occurs before the first occurrence of event B. Table 482.
PAGE 736
Intel® 413808 and 413812—PMON Unit 16.4.3 Incrementing By More Than 1 For scenarios where it is desired to increment a count by more than one on a single clock tick, the PMON unit can be sent a “bit encoded” value. This allows the counters to track an increment/decrement of up to 2N-1each clock tick, where N is the number of counters available. For example, with78 counters we could track an increment/decrement of up to 128 (2 ) each clock.
PAGE 737
PMON Unit—Intel® 413808 and 413812 16.4.4 Queue Analysis Example 9. Queue Depth Example This example demonstrates how to measure the current fill level (depth) of a particular queue. Table 483. Hardware Event Based Event Counting Example Opcode Write Event Register Start (CC is =) Sample Read Data Register Target Counter 0 0 0 0 Increment Event Decrement Event Queue enter Queue Exit Trigger Event Immed (000h) Immed (000h) Figure 113.
PAGE 738
Intel® 413808 and 413812—PMON Unit Example 10. Queue Depth Histogram Example This example demonstrates how to measure the current fill level (depth) of a particular queue. Table 484.
PAGE 739
PMON Unit—Intel® 413808 and 413812 Example 11. Head of Queue Histogram Example A histogram can be created using two counters working together. The following applies to all of the histogram examples: • Start with idle system (reset counters). • Only one slice of a histogram is measured per experiment, therefore histograms can only be generated for repeatable workloads. • Repeat these steps, changing threshold value and using an unchanging repeatable workload to generate data for histogram.
PAGE 740
Intel® 413808 and 413812—PMON Unit Figure 114.
PAGE 741
PMON Unit—Intel® 413808 and 413812 Figure 115.
PAGE 742
Intel® 413808 and 413812—PMON Unit In each of the 4 iterations above, the exact same repeatable workload produces identical queue behavior, but the Counter 1 value (called Condition Code Matches below) differs due to having a different threshold value each time. The condition code match values (10, 8, 4, 3) from the 4 iterations can be used to compute the values of a histogram as shown in the following two figures. Figure 116. Processing of HOQ Histogram Example B6318-01 Figure 117.
PAGE 743
PMON Unit—Intel® 413808 and 413812 16.5 Non-Register-Based Interfaces 16.5.1 Events Input Port 16.5.2 Output Signals This section describes the interfaces to the PMON unit that are not part of the register scheme already documented. Signals representing internal events are sent to the event preconditioning block where they are conditioned when required. The most common preconditioning is likely to be clock synchronization.
PAGE 744
Intel® 413808 and 413812—PMON Unit 16.5.2.1 Warning: Indicator Output The PMONOUT pin is a shared indicator output pin. The resulting signal allows external elements (OS, drivers, logic analyzer, etc.) to be aware of indicators without having to rely on interrupts. For 4138xx, the PMONOUT function is multiplexed onto the GPIO7 pin. When the PMON Indicator Output Enable bit is set in the “PMON Feature Enable Register PMONEN”, the PMON output function overrides the GPIO7 setting in the Section 15.2.
PAGE 745
PMON Unit—Intel® 413808 and 413812 16.5.3 T Internal Bus Addresses The Internal Bus Address Offset to PMMRBAR of any PMON Register can be derived by adding the 4 KB address aligned Internal Bus Memory Mapped Register Range Offset (Table 486, “PMON Internal Bus Memory Mapped Register Range Offsets” on page 745) to the Register Offset (Table 487, “PMON Register Summaries” on page 745) For example the offset to PMMRBAR of the “PMON Status Register - PMONSTAT” would be (4 E000H+044H) or 4 E044H. Table 486.
PAGE 746
Intel® 413808 and 413812—PMON Unit 16.5.4 PMON Feature Enable Register - PMONEN Contains control bits for PMON unit. Table 488.
PAGE 747
PMON Unit—Intel® 413808 and 413812 16.5.6 T PMON Memory Mapped Registers The memory mapped registers of PMON unit are accessible by the Intel XScale® core. The first set of registers provide the control of the PMON unit for selecting events to monitor and for data sampling. Each counter has one command, one events, one status, and one data register associated with it. These registers are numbered 0 through 7.
PAGE 748
Intel® 413808 and 413812—PMON Unit Table 491.
PAGE 749
PMON Unit—Intel® 413808 and 413812 16.5.6.1 PMON Command Register 0-7 - PMON_CMD[0:7] This 32-bit register allows control of the PMON counter. When this register is written, the previous register contents are overwritten. All 32 bits must be programmed each time the register is written. When the register contained a command that was still waiting to be triggered, it would be flushed without ever being executed.
PAGE 750
Intel® 413808 and 413812—PMON Unit Table 492.
PAGE 751
PMON Unit—Intel® 413808 and 413812 Table 492.
PAGE 752
Intel® 413808 and 413812—PMON Unit Table 492.
PAGE 753
PMON Unit—Intel® 413808 and 413812 16.5.6.2 PMON Event Register 0-7 - PMON_EVR[0:7] This 32-bit register contains the events that control the incrementing and decrementing of the PMON counter selected. When this register is written, the previous register contents are overwritten (the event fields are unbuffered) and the associated counter is immediately affected by the change.
PAGE 754
Intel® 413808 and 413812—PMON Unit 16.5.6.3 PMON Status Register 0-7 - PMON_STS[0:7] This 32-bit register reports the current status of the PMONx counter. Table 494.
PAGE 755
PMON Unit—Intel® 413808 and 413812 Table 494.
PAGE 756
Intel® 413808 and 413812—PMON Unit 16.5.6.4 PMON Data Register 0-7 - PMON_DATA[0:7] This 32-bit register allows for reading of the sampled value from PMON event counter X and contains the threshold value that is compared to the value in the event counter when a threshold condition (non-0 condition code) is in effect. Table 495.
PAGE 757
PMON Unit—Intel® 413808 and 413812 16.5.7 PMON Events PMON events can be selected for any of the counters. Each event is defined by a unique Event Selection Code (ESC) as defined below. For events which are duplicated within 4138xx with duplicate units (ADMA, SAS ports, etc.) source select field is used to select the unit the corresponding event is associated with. Event types are designated by Type, Occurrence only (O), Duration only (D) or events that can be selected as either (OD).
PAGE 758
Intel® 413808 and 413812—PMON Unit 16.5.7.2 Clock Events One of the clock events matches the frequency of the PMON unit clock. Software must comprehend that the frequency of this PMON unit clock may be different from one component to another. One piece of functionality this enables is to allow for event(s) to be counted during a fixed period of time. The Clock Event that matched the PMON Counter frequency can be used to trigger any command to execute.
PAGE 759
PMON Unit—Intel® 413808 and 413812 16.5.7.4 PCI Interface Events The PCI Interface Events apply to the ATU-X unit. Table 500. PCI Interface Events Event Selectio n Code (Hex) Event SRC Type Comment 680 PCI Inbound Data Transferred N D 681 PCI Inbound Rd Data Transferred N D 682 PCI Inbound Data Wr Transferred N D 683-687 reserved Count equals number of 8_byte data cycles (actual data transferred can be 1 to 8 bytes).
PAGE 760
Intel® 413808 and 413812—PMON Unit 16.5.7.5 PCI Express Interface Events The PCI Interface Events apply to the ATU-E unit. Table 501.
PAGE 761
PMON Unit—Intel® 413808 and 413812 16.5.7.6 North Internal Bus Events The North Internal Bus has multiple initiators. Some events apply to each requester unit and the following table represents the Source Select Field values for each unit. Table 502. North Internal Bus Source Select Summary Source Select Value 0 1 2 3:7 Port Intel XScale® Intel XScale® core 0 core 1 Internal Bus Bridge Reserved The events and corresponding codes for the North Internal Bus are defined in the following table.
PAGE 762
Intel® 413808 and 413812—PMON Unit 16.5.7.7 South Internal Bus Events The South Internal Bus has multiple initiators. Some events apply to each requester unit and the following table represents the Source Select Field values for each unit. Table 504. South Internal Bus Source Select Summary Source Select Value 0 1 2 3 4 5:7 Port ATU-E ATU-X Internal Bus Bridge Reserved Reserved Reserved The events and corresponding codes for the South Internal Bus are defined in the following table.
PAGE 763
Clocking and Reset—Intel® 413808 and 413812 17.0 Clocking and Reset This chapter describes the clocking and reset function of the Intel® 413808 and 413812 I/O Controllers in TPER Mode (4138xx). 17.1 Clocking Overview The 4138xxcontains various internal clocking boundaries. PLLs are used to generate the clocks. One PLL for the PCI Express interface, one for PCI-X interface, one for Memory Interface and one for everything else.
PAGE 764
Intel® 413808 and 413812—Clocking and Reset 17.1.1 Clocking Theory of Operation 17.1.1.1 Clocking Region 1 (PCI Express) 17.1.1.2 Each region within the 81348 contains different clocking requirements. These requirements are summarized in the following sections. Region 1 obtains its input clock from the PCI Express reference clock The REFCLK+/differential input supplies a 100 MHz clock for normal operation on the PCI Express interface. The analog front end for this region generates the 2.
PAGE 765
Clocking and Reset—Intel® 413808 and 413812 17.1.1.2.1 Central Resource Mode (PCIX_EP# = ‘1’) When operating as the Central Resource (PCIX_EP# = 1), the bus PCI bus operating frequency and default value in ATUX PCSR[19:16] is determined based on the sampling of PCIXCAP, P_MODE2, M66EN, PCIXM1_100#, and PCIXM2_100#. Table 506. PCI Bus Frequency Initializationa ATUX PCIXM2_100 PCI Bus Mode PCI Bus Frequency PCSR[19:16 P_PCIXCAP P_MODE2 P_M66EN PCIXM1_100 # # ] < 0.11VCC < 0.11VCC < 0.6VCC & > 0.11 VCC < 0.
PAGE 766
Intel® 413808 and 413812—Clocking and Reset 17.1.1.2.2 cPCI Hot-Swap Mode (PCIX_EP# = ‘0’ and HS_SM# = ‘0’) When operating in a Compact PCI Hot-Swap environment (HS_SM#=0, PCIX_EP#=0), the HS_FREQ[1:0] and P_M66EN pins are used to determine PCI Bus operating frequency and set default value in ATUX PCSR[19:16]. Inputs are sampled at trailing edge of reset and used to set dividers on region 2 PLL. Table 508.
PAGE 767
Clocking and Reset—Intel® 413808 and 413812 17.1.1.2.4 Secondary Clock Outputs This component has the ability to provide four PCI bus clocks (P_CLKO[3:0]) to drive external components as well as a dedicated feedback clock (P_CLKOUT) to drive the ATUX PCI interface. These clock outputs are can only be used when the PCI Express reference clock (REFCLK+/-) is used as the primary chip clock and the ATUX is enabled and configured to operate as a Central Resource. 1 Table 510.
PAGE 768
Intel® 413808 and 413812—Clocking and Reset 17.1.1.3 Clocking Region 3 (Internal Bus) Region 3 covers the 81348 internal bus and obtains is input clock from either REFCLK+/-or P_CLKIN defending on the setting of the CLK_SRC_PCIE# strap. Region 3 operates at a frequency up to 400 MHz. All units interface to or reside in this region. The units which interface to this region include the Intel XScale® processors, the Memory Controller Unit, ATU and bridge to the AHB bus.
PAGE 769
Clocking and Reset—Intel® 413808 and 413812 17.1.2 Clocking Region Summary Table 511 summarizes all of the input clock pins, output clock pins, and clock strapping option pins used in 81348. Table 511.
PAGE 770
Intel® 413808 and 413812—Clocking and Reset 17.2 17.2.1 Reset Overview Fundamental Reset There are four fundamental (hardware) resets for the 81348. The main power on reset is controlled through the PCI reset signal (P_RST#). When this signal is asserted, the entire I/O Processor is placed in a reset state. The other resets have differing behavior based on strapping options and chip mode. The reset straps are sampled at the exit of all fundamental resets.
PAGE 771
Clocking and Reset—Intel® 413808 and 413812 17.2.2 Software Reset In addition to the fundamental resets, 81348 provides software control to reset the internal bus, and Intel XScale processor. Reset straps are not re-sampled due to these resets. • Internal Bus Reset Bit — This reset can be initiated in two ways. The first is by writing to the coordinated reset bits in the MU Section 4.7.4, “Inbound Interrupt Status Register - IISR” on page 414.
PAGE 772
Intel® 413808 and 413812—Clocking and Reset 17.2.4 PCI Reset 17.2.5 PCI Express Hot Reset 17.2.6 WARM_RST# Reset Mechanism This is the primary reset input for both the PCI Express and PCI/X interfaces. The P_RST# reset clears all internal state machines and logic, and initialize all registers, including sticky bits, to their default states. The assertion and deassertion of the PCI reset signal P_RST# is asynchronous with respect to P_CLKIN/REFCLK+/-.
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Clocking and Reset—Intel® 413808 and 413812 17.2.7 Intel XScale® Processor Reset Mechanism This reset is initiated through: • the HOLD_X0_IN_RST# /HOLD_X1_IN_RST# straps • the ATUX — Section 2.14.41, “PCI Configuration and Status Register - PCSR” on page 178 • the ATUE — Section 3.17.41, “PCI Configuration and Status Register - PCSR” on page 327.
PAGE 774
Intel® 413808 and 413812—Clocking and Reset 17.2.8 Internal Bus Reset This reset can be initiated through: • The coordinated reset bits in the MU Section 4.7.4, “Inbound Interrupt Status Register - IISR” on page 414. • The watchdog timer as described in Section 11.1.2, “Watch Dog Timer Operation” on page 629. This function resets the Intel XScale processor and all units on the internal bus, while preserving the PCI Configuration Registers.
PAGE 775
Clocking and Reset—Intel® 413808 and 413812 When the reset internal bus bit in the PCI Configuration and Status Register is set, there are sideband signals notifying the ATUX and MCU that a reset is coming. Table 514, “Internal Bus Reset Summary” describes the operation of each unit: Table 513. Internal Bus Reset Control Bit Locations Unit MU Coordinated Reset IRCSR[1] Selective Reset IRSCR[0] Table 514.
PAGE 776
Intel® 413808 and 413812—Clocking and Reset Table 514. Internal Bus Reset Summary (Sheet 2 of 2) Unit ATUE Preparation for Reset The ATUE does not participate in the IB Reset handshake. However the affect on the ATUE varies depending on the PCIE_RC# strap. End Point Mode (PCIE_RC# = 1): An Internal Bus Reset does not reset the ATUE when operating as an endpoint. Root Complex Mode (PCIE_RC# = 0) No special requirements, the ATUE can be reset at anytime. This reset includes the configuration space.
PAGE 777
Clocking and Reset—Intel® 413808 and 413812 17.3 Reset Pins Table 515. Reset Pin Summary Pin Input/Output P_RST# Input WARM_RST# Input Description Primary chip reset. Should be connected to PCI RST# or PCI Express PERST# depending on the mode of operation. Warm Reset is the same as a cold reset, except sticky configuration bits are not reset. This pin should only be used when the sticky bit functionality is required.
PAGE 778
Intel® 413808 and 413812—Clocking and Reset 17.4 Device Function Select In all cases, the INTERFACE_SEL_PCIX# strap affects whether the part operates as a PCI Express or PCI-X device. Table 516. TPER Mode Per Function Storage Port Allocation (CONTROLLER_ONLY#=1) DF_SEL[2:0] 000 001 010 011 100 101 110 111 Intel® 413808 and 413812 I/O Controllers in TPER Mode Function 0 Function 1 ATU TPMI1 8 n/a Reserved Table 517.
PAGE 779
Clocking and Reset—Intel® 413808 and 413812 17.5 Reset Strapping Options Note: See Datasheet and/or Design Guide for details on how to configure reset straps. Table 518, “Reset Strap Signals” on page 780 details the reset strapping options that are available to configure the component during reset. These straps are sampled and the component operating mode is determined at the deassertion of the fundamental reset.
PAGE 780
Intel® 413808 and 413812—Clocking and Reset Table 518. Reset Strap Signals (Sheet 1 of 2) Name Description PBI Boot Bus Width: Indicates default bus width for the PBI Memory Boot window. 0 = 8 bits wide (Requires pull-down resistor) 1 = 16 bits wide (Default mode) Device Function Select: DF_SEL[2:0] See Section 17.4, “Device Function Select” for additional details. Controller only enable CONTROLLER_ONLY# 0 = Controller Only. Non-TPER Mode. 1 = TPER mode.
PAGE 781
Clocking and Reset—Intel® 413808 and 413812 Table 518. Reset Strap Signals (Sheet 2 of 2) Name EXT_ARB# PCIX_32BIT# HS_SM# SMB_A5 SMB_A3 SMB_A2 SMB_A1 PCIX_PULLUP# FW_TIMER_OFF# CLK_SRC_PCIE# LK_DN_RST_BYPASS# October 2007 Order Number: 317805-001US Description External Arbiter: Determines wether the PCI interface enables the integrated arbiter, or uses an external arbiter.
PAGE 782
Intel® 413808 and 413812—Test Logic Unit and Testability 18.0 Test Logic Unit and Testability 18.1 Overview This chapter summarizes testability and configuration features incorporated in the Intel 413808 and 413812 I/O Controllers in TPER Mode (4138xx). The 4138xx test and control logic is based on the IEEE 1149.1-2001 Standard Test Access Port and Boundary-Scan Architecture document (available from the IEEE). The TAP controller supports on-chip test logic such as Built-In Self Test and boundary-scan.
PAGE 783
Test Logic Unit and Testability—Intel® 413808 and 413812 18.2 IEEE 1149.1 Standard Test Access Port (TAP) The I/O processor contains test logic that is compatible with the IEEE Standard 1149.1-2001 Test Access Port (TAP) and Boundary Scan Architecture. Logic that conforms to this standard contains: • Test Access Port (TAP): — four inputs (TDI, TMS, TRST# and TCLK) — single output (TDO). • TAP controller • Instruction register • Group of test data registers Each of these is described in more detail below.
PAGE 784
Intel® 413808 and 413812—Test Logic Unit and Testability 18.2.1 TAP Pin Description 18.2.1.1 Test Clock (TCK) 18.2.1.2 18.2.1.3 18.2.1.4 18.2.1.5 The internal test logic is accessed through the TAP pins. The following sections describe some of the rules and permissions of the IEEE 1149.1a Standard for the TAP pins. This is the clock input for the test logic defined by this standard, i.e. the TAP controller and associated registers.
PAGE 785
Test Logic Unit and Testability—Intel® 413808 and 413812 18.2.2 TAP Controller The TAP controller, shown in Figure 122, is a sixteen-state synchronous finite state machine that changes state on the rising edge of TCK. The controller’s next state is controlled by the state present at the TMS input.
PAGE 786
Intel® 413808 and 413812—Test Logic Unit and Testability 18.2.2.1 Test-Logic-Reset State In this state, test logic is disabled to allow normal operation of the Intel XScale processor. This is achieved by loading the instruction register with the IDCODE instruction. No matter what he state of the controller, it enters Test-Logic-Reset state when the TMS input is held high for at least five rising edges of TCK. The controller remains in this state while TMS is high.
PAGE 787
Test Logic Unit and Testability—Intel® 413808 and 413812 18.2.2.5 18.2.2.6 18.2.2.7 18.2.2.8 18.2.2.9 Shift-DR State In this controller state, the test data register, which is connected between TDI and TDO as a result of the current instruction, shifts data one bit position nearer to its serial output on each rising edge of TCK. Test data registers that the current instruction select but do not place in the serial path, retain their previous value during this state.
PAGE 788
Intel® 413808 and 413812—Test Logic Unit and Testability 18.2.2.10 Select-IR-Scan State This is a temporary controller state. Here the decision is made to enter the Capture-IR column and initiate a scan sequence for the instruction register or to return to Test-Logic-Reset. All test data registers selected by the current instruction retain their previous value during this state. Transition to next state: When TMS is low on the rising edge of TCK, move to Capture-IR, else move to Test-Logic-Reset. 18.2.2.
PAGE 789
Test Logic Unit and Testability—Intel® 413808 and 413812 18.2.2.15 Exit2-IR State This is a temporary state. All test data registers selected by the current instruction retain their previous value during this state. The instruction does not change while the TAP controller is in this state. Transition to next state: When TMS is held high during the next rising edge of TCK, the controller enters the Update-IR state and the scanning process terminates.
PAGE 790
Intel® 413808 and 413812—Test Logic Unit and Testability 18.2.3 TAP Controller Registers 18.2.3.1 Instruction Register The IEEE 1149.1 architecture specifies a minimum or two test data registers: bypass and boundary scan. The IOP TAP controller extends this number to allow access to test features within the device. Some registers are for public use, others are private. Per the standard, each test data register has a fixed length and can be accessed using one or more instructions.
PAGE 791
Test Logic Unit and Testability—Intel® 413808 and 413812 18.2.3.2 Instructions Each of the TAP controller instruction sets is composed of both public and private instructions. Public instructions are intended for use by purchasers of the part. Since the instruction set for each TAP controllers is independent of one another, each is listed separately below Table 519.
PAGE 792
Intel® 413808 and 413812—Test Logic Unit and Testability 18.2.3.3 18.2.3.4 18.2.3.5 Boundary-Scan Register Boundary-Scan Register is a set of serial-shiftable register cells, connected between each system pin and on-chip system logic. (Power, ground and TAP pins excluded.) This forms a single shift register between TDI and TDO of all the system pins. This is the most extensive, complex register in the test circuitry. This register allows testing of circuitry external to the component (e.g.
PAGE 793
Test Logic Unit and Testability—Intel® 413808 and 413812 18.3 Definition of Terms High-Z: ONCE: October 2007 Order Number: 317805-001US An instruction defined by the IEEE 1149.1 Standard. The requirement for this instruction are 1) all system logic outputs are high impedance; 2) the TAP controller continues to operate with the bypass register connected between TDI and TDO. The part may have other settings, as long as they do not interfere with these two requirements.
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Intel® 413808 and 413812—Peripheral Registers 19.0 Peripheral Registers This chapter summarizes the registers for the integrated peripherals. Each register is defined in detail in the corresponding unit chapter. 19.1 Overview Intel 413808 and 413812 I/O Controllers in TPER Mode (4138xx) Peripheral Registers can be accessed via three methods: • PCI Configuration Register interface: Is supported by the PCI interface and PCI Configuration Cycle transaction type.
PAGE 795
Peripheral Registers—Intel® 413808 and 413812 19.2 Accessing Peripheral Memory-Mapped Registers The PMMR interface is a slave device connected to the 4138xx internal bus. This interface accepts data transactions which appear on the internal bus from the ATU and the Intel XScale processors. The PMMR interface allows these devices to perform read, write, or read-modify-write transactions.
PAGE 796
Intel® 413808 and 413812—Peripheral Registers 19.5 Default Memory Space Setup Figure 124 shows the Intel XScale processor address space and addresses available to the applications. Figure 124 also shows the default locations of certain resources after reset. The PMMR Block occupies 512 KBytes of space and is located at addresses 0 FFD8 0000H through 0 FFDF FFFFH. Do not change the default address of the PMMR block.
PAGE 797
Peripheral Registers—Intel® 413808 and 413812 Figure 124.
PAGE 798
Intel® 413808 and 413812—Peripheral Registers 19.6 Warning: Peripheral Memory-Mapped Register Address Space The PMMR address space is divided to support the integrated peripherals on the 4138xx. Table 523 shows all of the 4138xx integrated peripheral memory-mapped registers and their internal bus address offsets. The starting address of the memory-mapped registers is programmable using the PMMRBAR register. The PMMRBAR register is located at a fixed location which is at F_FFFF_FFFCH.
PAGE 799
Peripheral Registers—Intel® 413808 and 413812 Table 523. Local Addresses for Integrated Peripherals (Sheet 2 of 3) Integrated Peripheral “GPIO” Not Claimed by any Unit “I2C Unit” 0 “I2C Unit” 1 “I2C Unit” 2 Reserved. Not Claimed by any Unit Reserved Reserved Not Claimed by any Unit “Messaging Unit” Not Claimed Reserved. Reserved.
PAGE 800
Intel® 413808 and 413812—Peripheral Registers Table 523. Local Addresses for Integrated Peripherals (Sheet 3 of 3) Internal Address Offset (Relative to PMMRBAR) Integrated Peripheral Not Claimed by any Unit +5 3800H through 5 3BFFH Not Claimed by any Unit +5 3C00H through 5 3FFFH Reserved. +6 0000H through 6 1FFFH Reserved. +6 2000H through 6 3FFFH Reserved. +6 4000H through 6 5FFFH Reserved.
PAGE 801
Peripheral Registers—Intel® 413808 and 413812 19.6.1 Internal Units 19.6.1.1 Peripheral Bus Interface Unit Note: The Peripheral Bus Interface Unit (PBI) is allocated 128 Bytes of PMMR registers space and is always located at offset +1580H relative to the PMMRBAR. Use the following equation to calculate the actual register address: Internal Bus Address = PMMRBAR + PBI Base Address Offset + Register Offset.
PAGE 802
Intel® 413808 and 413812—Peripheral Registers 19.6.1.2 System Controller The System Controller Unit (SC) is allocated 16 Bytes of PMMR register space and is always located at offset +1640H relative to the PMMRBAR. Use the following equation to calculate the actual register address: Internal Bus Address = PMMRBAR + SC Base Address Offset + Register Offset. Table 526. SC Base Address Offset. Unit SC Base Address Offset (Relative to PMMRBAR) System Controller +1640H Table 527.
PAGE 803
Peripheral Registers—Intel® 413808 and 413812 19.6.1.4 Note: I/O Pad Control The I/O Pad Control is allocated 512 Bytes of PMMR registers space and is always located at offset +2000H relative to the PMMRBAR. Use the following equation to calculate the actual register address: Internal Bus Address = PMMRBAR + I/O Pad Control Base Address Offset + Register Offset. The PBI drive strength register is described in the Peripheral Bus Interface chapter. Table 530. I/O Pad Control Base Address Offset.
PAGE 804
Intel® 413808 and 413812—Peripheral Registers 19.6.1.5 UART 0-1 The 4138xx contains two instances of the UART. Each UART is allocated 64Bytes of PMMR registers space that is located at the offset specified in Table 532 which is relative to the PMMRBAR. Use the following equation to calculate the actual register address: Internal Bus Address = PMMRBAR + UART Base Address Offset + Register Offset. Table 532. UART 0-1 Offset.
PAGE 805
Peripheral Registers—Intel® 413808 and 413812 19.6.1.6 GPIO The GPIO block is allocated 64Bytes of PMMR registers space that is located at the offset specified in Table 535 which is relative to the PMMRBAR. Use the following equation to calculate the actual register address: Internal Bus Address = PMMRBAR + GPIO Base Address Offset + Register Offset. Table 534. GPIO Offset. Unit GPIO Base Address Offset Relative to PMMRBAR) GPIO +2480H Table 535.
PAGE 806
Intel® 413808 and 413812—Peripheral Registers 19.6.1.8 Messaging Unit The Messaging Unit (MU) is allocated 8 KBytes of PMMR registers space that is located at the offset specified in Table 538 which is relative to the PMMRBAR. Use the following equation to calculate the actual register address: Internal Bus Address = PMMRBAR + MU Base Address Offset + Register Offset. Table 538. Messaging Unit Offset. Unit MU Base Address Offset (Relative to PMMRBAR) Messaging Unit Table 539.
PAGE 807
Peripheral Registers—Intel® 413808 and 413812 Table 539.
PAGE 808
Intel® 413808 and 413812—Peripheral Registers 19.6.1.9 PMON Unit The PMON Unit (PMON) is allocated 8 KBytes of PMMR registers space that is located at the offset specified in Table 540 which is relative to the PMMRBAR. Use the following equation to calculate the actual register address: Internal Bus Address = PMMRBAR + PMON Base Address Offset + Register Offset. Table 540. PMON Unit Base Address Offset. Unit PMON Unit PMON Base Address Offset (Relative to PMMRBAR) Table 541.
PAGE 809
Peripheral Registers—Intel® 413808 and 413812 19.6.2 Host Interface Units This section describes the register layout of the units that are visible as PCI functions. These units include the TPMI0-3, ATUE and ATUX. The PCI Function number for each of these units vary based on strapping options that are sampled during reset. The PCI Function number associated with each unit and its Base Address Offset are detailed in Table 542, “PCI Function MMR Locations” Table 542.
PAGE 810
Intel® 413808 and 413812—Peripheral Registers 19.6.2.1 Note: T Address Translation Unit (PCI-X) A subset of the ATU registers are accessible through both inbound PCI configuration cycles and the 4138xx core CPU (Register offsets 000H through 0FFH). The balance of the registers are accessible only via the internal bus.
PAGE 811
Peripheral Registers—Intel® 413808 and 413812 Table 544.
PAGE 812
Intel® 413808 and 413812—Peripheral Registers Table 544.
PAGE 813
Peripheral Registers—Intel® 413808 and 413812 Table 544.
PAGE 814
Intel® 413808 and 413812—Peripheral Registers 19.6.2.2 Note: Address Translation Unit (PCI-E) All of the ATU registers are accessible through both inbound PCI configuration cycles and the 4138xx core CPU (Register offsets 000H through FFFH).
PAGE 815
Peripheral Registers—Intel® 413808 and 413812 Table 546.
PAGE 816
Intel® 413808 and 413812—Peripheral Registers Table 546.
PAGE 817
Peripheral Registers—Intel® 413808 and 413812 Table 546.
PAGE 818
Intel® 413808 and 413812—Peripheral Registers Table 546. Address Translation Unit Registers — ATUE (Sheet 4 of 4) Register Description (Name) Inbound Vendor Defined Message Payload Register — IVMPR Reserved. Outbound Vendor Defined Message Header Register0 — OVMHR0 Outbound Vendor Defined Message Header Register 1 — OVMHR1 Outbound Vendor Defined Message Header Register 2 — OVMHR2 Outbound Vendor Defined Message Header Register 3 — OVMHR3 Outbound Vendor Defined Message Payload Register — OVMPR Reserved.
PAGE 819
Peripheral Registers—Intel® 413808 and 413812 19.7 PCI Configuration Space The PCI Configuration space of the 4138xx varies depending on the DFSEL, INTERFACE_SEL_PCIX#, and CONTROLLER_ONLY# straps. The PCI Functions that are visible in via configuration transactions are details in Table 547, “Intel® 413808 and 413812 I/O Controllers in TPER Mode PCI Function Visibility”.
PAGE 820
Intel® 413808 and 413812—Peripheral Registers Table 549.
PAGE 821
Peripheral Registers—Intel® 413808 and 413812 Table 549.
PAGE 822
Intel® 413808 and 413812—Peripheral Registers Table 549.
PAGE 823
Peripheral Registers—Intel® 413808 and 413812 Table 549.
PAGE 824
Intel® 413808 and 413812—Peripheral Registers Intel® 413808 and 413812 I/O Controllers in TPER Mode Developer’s Manual 824 October 2007 Order Number: 317805-001US