user manual

ManualsBrandsIntel ManualsComputer HardwareComputer Hardware cpci borard with a intel pentuim M

Diversified Technology, Inc.

CPB4612

Configuration and Maintenance

Guide

Rev 1.2

CPB4612 CPCI Board

with a Intel® Pentium® M

United States of America. No part of this publication may be reproduced, stored in a

retrieval system, or transmitted, in any form or by any means, electronic,

mechanical, photocopying, recording, or otherwise without prior permission of the

publisher.

Summary of content (104 pages)

PAGE 1
Diversified Technology, Inc. CPB4612 Configuration and Maintenance Guide Rev 1.2 CPB4612 CPCI Board with a Intel® Pentium® M © Copyright 2005 by Diversified Technology, Inc. All rights reserved. Printed in the United States of America. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise without prior permission of the publisher.
PAGE 2
CPB4612 Configuration and Maintenance Guide Return Shipment Information If service or repair is required, contact DTI’s Service Department for a Return Material Authorization (RMA) number and shipping instructions. If the product is out of warranty, or was damaged during shipment, a purchase order will be required for the repair. The product should be returned in its original shipping materials. Contact DTI if replacement material is required.
PAGE 3
CPB4612 Configuration and Maintenance Guide For Your Safety CAUTION: The cPB-4612 contains a lithium battery. This battery is not field-replaceable. There is a danger of explosion if the battery is incorrectly replaced or handled. Do not disassemble or recharge the battery. Do not dispose of the battery in fire. When the battery is replaced, the same type or an equivalent type recommended by the manufacturer must be used. Used batteries must be disposed of according to the manufacturer's instructions.
PAGE 4
CPB4612 Configuration and Maintenance Guide Revision History Date Revision Summary of Corrections 08/31/04 1.0 Initial Release 10/12/04 1.1 Added links throughout manual. 8/19/05 1.2 Removed references to ethernet signal routing.
PAGE 5
CPB4612 Configuration and Maintenance Guide Table of Contents Return Shipment Information ...................................................................................................................................ii For Your Safety ...................................................................................................................................................... iii Revision History ...................................................................................................
PAGE 6
CPB4612 Configuration and Maintenance Guide 2.8 Operating System Installation...........................................................................................................................17 3 CONFIGURATION .................................................................................................... 19 3.1 Switch Descriptions ............................................................................................................................................21 3.1.
PAGE 7
CPB4612 Configuration and Maintenance Guide 7.3.2 Preload Value 2 (BAR+04h)..............................................................................................................................35 7.3.3 General Interrupt Status (BAR+08h) .................................................................................................................36 7.3.4 Reload Register (BAR+0Ch) ......................................................................................................................
PAGE 8
CPB4612 Configuration and Maintenance Guide B.2 J15 (CompactPCI Bus Connector)....................................................................................................................71 B.3 J11 (CompactPCI Bus Connector)....................................................................................................................72 B.4 J8 (CompactPCI Connector) .............................................................................................................................
PAGE 9
CPB4612 Configuration and Maintenance Guide Tables Jumper Cross-Reference Table........................................................................................................................ 20 Connector Assignments .................................................................................................................................... 68 J15 CompactPCI Bus Connector Pin out..........................................................................................................
PAGE 10
CPB4612 Configuration and Maintenance Guide Document Organization This document describes the operation and use of the CPB-4612 Computer Processor Board with an Intel® Pentium® M. The following topics are covered in this document. Chapter 1, "Introduction," introduces the key features of the CPB-4612. This chapter includes a product definition, a list of product features, and a functional block diagram with a brief description of each block.
PAGE 11
Chapter 1 1 Introduction This chapter provides an introduction to the CPB-4612 including a product definition, a list of product features, and a functional block diagram with descriptions of each block. The "cPB-4612 Faceplate" illustration identifies the connectors, indicators, and switches available on the cPB-4612's faceplate. Optional rear-panel transition boards are available to extend various faceplate features to a system's rear-panel.
PAGE 12
1.1 Product Definition The cPB-4612 Computer Processor Board is a single board computer designed to work as a modular component in a CompactPCI system. It utilizes the Intel® Pentium® M processor in a micro FCBGA package along with dual Gigabit Ethernet controllers and the latest in memory and I/O technology to provide an inexpensive, yet fast and reliable PICMG 2.16 board. The cPB-4612 is CompactPCI Packet Switching Backplane (CompactPCI/PSB) compatible and draws its power from the J1 and J2 connectors.
PAGE 13
CPB-4612 Faceplate Ejector Handle 10/100 Ethernet COM RS-232 Serial Port USB PMC PMC Reset Switch Hotswap LED Ejector Handle 3
PAGE 14
1.2 Features There are two SKU's of the cPB-4612. The first is the cPB-4612, which has a 64bit/66Mhz PMC site and a 32bit/33Mhz PMC site. . The second is the cPB-4612 w/ IDE, which has a 64bit/66Mhz PMC site and an on-board 2.5” HDD IDE connector. Other features include: • • • • • • • • • • • • • • • • • • • • • 1.3 CompactPCI Specification, PICMG 2.0, Version 2.1** compliant CompactPCI Specification, PICMG 2.16, Version 1.
PAGE 15
Functional Block Diagram 1.3.1 CompactPCI/PSB Architecture The cPB-4612 is designed to operate in a PICMG 2.0 CompactPCI backplane. If the system is placed in a system slot, the bridge will automatically configure itself as a transparent bridge, and the board will perform as the host. If the board is placed in a peripheral slot, the bridge will automatically configure itself as a nontransparent bridge, and the board will perform as a peripheral device.
PAGE 16
system's fabric-switched Link Ports A and B, and can be inserted into system or peripheral slots. The cPB4612 is keyed for insertion into compatible slots. The "CompactPCI" topic in Appendix D contains a link to the PCI Industrial Computer Manufacturers Group. 1.3.2 Processor The cPB-4612 uses the Mobile Pentium M in a micro FCBGA package. The 1MB or 2MB on-die transfer L2 cache is integrated with the CPU, eliminating the need for separate components and improving performance.
PAGE 17
1.3.5 Memory and I/O Addressing The cPB-4612 supports up to 2GB of DDR333/266/200 via two right-angled SODIMM sockets. Memory can be purchased from DTI separately. See the "Memory Configuration" and "I/O Configuration" topics in Chapter 2 for more information. 1.3.6 Power Ramp Circuitry The cPB-4612 features a power controller with power ramp circuitry that allows the board's voltages to be ramped in a controlled fashion.
PAGE 18
Access Controller (MAC) and the physical layer (PHY) interface combined into a single component solution. Both Ethernet Channels are directed to the rear connector at J3 for PICMG 2.16 support. The "Ethernet" topic in Appendix D contains links to the datasheets for the Ethernet devices used on the cPB-4612. 1.3.11 10/100 Ethernet Interface The cPB-4612 supports one 10/100 Base-TX Ethernet interface. The Intel 82559EM Ethernet controller provides this interface.
PAGE 19
• Real-Time Clock • On-board PCI devices Enhanced capabilities include the ability to configure each interrupt level for active high-going edge or active low-level inputs. The cPB-4612's interrupt controllers reside in the 6300ESB device. The "Intel 855GME Chipset" topic in Appendix D provides a link to the datasheet for this device. 1.3.15 Counter/Timers Three 8254-style counter/timers, as defined for the PC/AT, are included on the cPB-4612.
PAGE 20
1.3.20 Universal Serial Bus (USB) The Universal Serial Bus (USB) provides a common interface to slower-speed peripherals. Functions such as keyboard, serial ports, printer port, and mouse ports can be consolidated into USB, simplifying cabling requirements. The cPB-4612 provides one USB port at its faceplate (connector J20 is Port 0). USB Port 1 and USB port 2 are routed to the cPB-4612’s J5 Rear Panel I/O connector. The cPB-4612’s USB channels are controlled by the Intel 6300ESB device.
PAGE 21
Chapter 2 2 Getting Started This chapter summarizes the information needed to make the cPB-4612 operational. This chapter should be read before using the board.
PAGE 22
2.1 Unpacking Check the shipping carton for damage. If the shipping carton and contents are damaged, notify the carrier and DTI for an insurance settlement. Retain the shipping carton and packing material for inspection by the carrier. Obtain authorization before returning any product to DTI. Refer to the Return Shipment Information page for assistance. CAUTION: This board must be protected from static discharge and physical shock.
PAGE 23
Configuration 5V (avg) 5V (peak) 3.3V (avg) 3.3V (peak) 12V (avg) 12V (peak) -12V (avg) -12V (peak) 1.7GHz / 512MB 6.9A TBD* 2.4A TBD* 20mA 50mA 0.0A 0.0A Hard disk (add) (typical) 540mA 1.00A N/A N/A N/A N/A N/A N/A PMC card typical1 (add) 1.00A 1.70A 0.75A 1.30A 100mA 200mA 20mA 40mA PMC card max.2 (add) 1.50A 3.00A 2.25A 4.
PAGE 24
Memory Address Map Example 4 GB FFF80000h - FFFFFFFFh SYSTEM BIOS/Flash 4 GB - 512 KB 8000000h - FFF7FFFFh PCI PERIPHERALS 100000h - 1FFFFFFFh SYSTEM MEMORY 512 MB 1 MB E0000h - FFFFFh SYSTEM BIOS 896 KB C8000h - DFFFFh BIOS EXTENSION C0000h - C7FFFh VGA BIOS 800 KB A0000h - BFFFFh VGA DISPLAY MEMORY 768 KB LOCAL DRAM 0 0h - 9FFFFh 14 640 KB
PAGE 25
2.4 I/O Configuration The cPB-4612 addresses up to 64 KB of I/O using a 16-bit I/O address. The cPB-4612 is populated with many commonly used I/O peripheral devices. The I/O address location for each peripheral is shown in the "I/O Address Map" illustration. I/O Address Map D00 - FFFFh PCI* *Onboard ISA peripherals CF8 - CFFh PCI Config/RST Control addressed between 780 - CF7h PCI Reserved 100h - 7FFh decode 11 bits 778 - 77Fh LPT ECP Registers of address (A0h - A10h).
PAGE 26
80h 2.5 Diagnostic Port 78 - 79h Reserved 70 - 77h On-board Real-Time Clock 60 - 6Fh Keyboard and System Ports 50 - 5Fh Reserved 40 - 4Fh On-board Timer/Counters 30 - 3Fh Reserved 2E - 2Fh Super I/O Configuration 22 - 2Dh Reserved 20 - 21h On-board master Interrupt Controller 0 - 1Fh On-board Master DMA Controller Connectors The cPB-4612 includes several connectors to interface to application-specific devices.
PAGE 27
Setup Screen SYSTEM CONFIGURATION SUMMARY SYSTEM SUMMARY Diversified Technology, Inc – cPB4612 SYSTEM SETUP CPU Type HARD DISK SETUP BOOT ORDER :Intel(R) Pentium(R) M processor 1700MHz CPU Speed : 1.70GHz Hard Disk 0: Not Detected L2Cache : 1024KB Hard Disk 1: Not Detected : 639K Hard Disk 2: Not Detected Base RAM Extended RAM: 480MB PERIPHERALS Video RAM : 32MB Hard Disk 3: Not Detected COM Ports : 3F8 2F8 3E8 PCB Revision: 1.
PAGE 28
5. Proceed with the OS installation as directed, being sure to select appropriate device types if prompted. Refer to the appropriate hardware manuals for specific device types and compatibility modes of DTI products. 6. When installation is complete, reboot the system and set the boot device order in the SETUP boot menu appropriately.
PAGE 29
Chapter 3 3 Configuration The cPB-4612 has been designed for maximum flexibility. Many features can be configured by the user for specific applications. Most configuration options are selected through the BIOS Setup utility (discussed in the "BIOS Configuration Overview" topic in Chapter 2). Some options cannot be software controlled and are configured with jumpers.
PAGE 30
Jumper Options and Locations The cPB-4612 contains a push-button switch on the faceplate and eight jumpers on the component side of the board. The jumpers are listed and briefly described in the "Jumper Cross-Reference" table below. Factory default switch settings are shown in the "Default Jumper Settings" figure.
PAGE 31
Default Jumper Configuration 3.1 Switch Descriptions The following topics list the switches in numerical order and provide a detailed description of each switch. 3.1.1 PB1 (Reset) PB1 is a push-button on the front of the cPB-4612. Pressing PB1 issues a hard reset. Reset is discussed in more detail in Chapter 4. 3.1.2 J16-1 (BKT-GND to GND) Installing this jumper will short the bracket ground to digital ground. This may positively or negatively affect EMI emissions, depending on the system.
PAGE 32
3.1.3 J16-2 (+12V to J5-pin D1). Installing this jumper will connect +12V to the CompactPCI connector J5, pin D1. This is only to be used for specially designed RTM cards that may need it. The default is for no jumper. J16-2 Open Function Default Closed CPCI J5-pin D1 is a no connect. CPCI J5-pin D1 is shorted to +12V. 3.1.4 J16-3 (+5V PMC I/O) Installing this jumper sets the 32bit/33Mhz PMC site’s VI/O voltage to +5V. Having no jumper sets the VI/O voltage to 3.3V.
PAGE 33
3.1.8 J17-3 (Disable Onboard Video) Installing this jumper will disable the onboard video. Place this jumper if using a PCI video card only. J17-3 Open Function Default Closed Onboard video is enabled. The onboard video is disabled. 3.1.9 J17-4 (Manufacture Test Mode) Used by DTI for testing purposes. Do not install a jumper at this location. J17-4 Open Closed Function Default Normal operation Board in manufacturing test mode. 3.1.
PAGE 34
Chapter 4 4 Reset This chapter discusses the reset types and reset sources on the cPB-4612. If necessary, the cPB-4612’s board reset characteristics can be tailored to the requirements of a specific system.
PAGE 35
4.1 Reset Types and Sources The cPB-4612’s reset types are listed below. The sources for each reset type are detailed in the following topics. • Hard Reset: All devices are held in reset. • Soft Reset: CPU initialization only. Other devices are not reset. • Backend Power Down: The backend logic is powered off. The board is powered on and is held in reset. • NMI: Non-maskable interrupt. Though not a reset in the strict sense, an NMI can have the same effect as other resets. 4.1.
PAGE 36
4.1.4 NMI Sources Watchdog Timer (System Register Address 79h) The watchdog timer may be programmed to generate a non-maskable interrupt if it is not strobed within a given time-out period. This function is discussed in Chapter 7, "Watchdog Timer.
PAGE 37
Chapter 5 5 System Monitoring and Control The cPB4612 has an IPMI System Monitor that complies with PICMG® 2.9 specification, and complies with IPMI Specification 1.5. This allows a PICMG 2.9 compliant chassis that utilizes a chassis manager, or Baseboard Management Controller (BMC) to detect the presence of the cPB4612 and make Field Replaceable Unit (FRU) information, and Sensor Device Records (SDR’s) available.
PAGE 38
5.1 Monitoring and Control Functions The IPMI System Monitor has a dedicated serial interface to the host processor on the cPB4612. It is a 16550-compatible UART that is configurable in SETUP. If this interface is not required, it can be disabled. Otherwise, it will be given a unique serial port address and interrupt. Note that the interrupt cannot coincide with the other COM ports; it is not shareable. The serial interface is fixed at 9600 baud, 8 data bits, 1 stop bit, no parity, full duplex.
PAGE 39
5.3 Field Replaceable Unit (FRU) Information Board information, such as serial number, date of manufacture, OEM name, part number, etc., are retrievable from the FRU. It complies with the IPMI FRU 1.0 Specification. The information in the FRU can be customized to add other product information, such as asset tag, other part numbers, etc. 5.4 Sensors The sensors that the cPB4612 supports with the IPMI System Monitor can be retrieved in the Sensor Data Records (SDR’s) via normal IPMI commands.
PAGE 40
Chapter 6 6 IDE Controller The cPB-4612 with IDE has an on-board IDE controller that provides two IDE channels for interfacing with up to four IDE devices. The IDE controller is incorporated into the Intel 6300ESB, which supports ATA100. There is one 50-pin IDE connector on the cPB-4612 with IDE, which supports up to two IDE devices (though there is only space on the board itself to mount one device). The secondary IDE channel is available through the rear panel connector (J5).
PAGE 41
6.1 • • • • • • 6.2 Features of the IDE Controller Primary and Secondary channels for interfacing up to four devices IBM-AT compatible Supports PIO and Bus Master IDE "Ultra ATA/33/66/100" Synchronous DMA Operation Bus Master IDE transfers up to 100 MB/sec. Individual software control for each IDE channel Disk Drive Support The cPB-4612 supports internal and external IDE devices. These configurations are described below. 6.2.
PAGE 42
Chapter 7 7 Watchdog Timer This chapter explains the operation of the cPB-4612’s watchdog timer. It provides an overview of watchdog operation and features, as well as sample code to help you learn how the watchdog timer works with applications.
PAGE 43
7.1 Watchdog Timer Overview The watchdog timer is implemented by using the 6300ESB ICH integrated watchdog timer. The primary function of the watchdog timer is to monitor the cPB-4612’s operation and take corrective action if the software fails to function as programmed.
PAGE 44
7.2.2 WDT Configuration Register (60h) Offset: 60-61h Default Value: 00h Size: 16 bits Attribute: R/W Bit Description 15-6 Reserved 5 WDT_OUTPUT: Output Enable This bit indicates whether or not the WDT will toggle the WDT_TOUT# pin if the WDT times out. 4-3 2 Reserved WDT_PRE_SEL: Prescaler Select The WDT provides two options for prescaling the main down counter. The preload values are loaded into the main down counter right justified.
PAGE 45
Bit 7:3 2 Description Reserved WDT_TOUT_CNF: Timeout configuration 0 – Watchdog Timer Mode 1 – Free Running Mode 1 WDT_ENABLE: Watchdog Enable 0 – Disabled 1 - Enabled 0 WDT_LOCK Setting this bit will lock values of this register until a hard reset occurs or power is cycled. 0 – Unlocked 1 - Locked 7.3 Memory Mapped Registers The following registers control the preload values and reload status of the watchdog timer controller.
PAGE 46
Bit Description 31:20 Reserved 19:0 Preload_Value_2 7.3.3 General Interrupt Status (BAR+08h) Offset: BAR+08h Default Value: 00h Size: 8 bits Attribute: R/WC Bit 7:1 0 Description Reserved Watchdog Timer Interrupt Active This bit is set when the first stage of the 35 bit down counter reaches zero. This is a sticky bit and is cleared by writing a ‘1’. 0 – No Interrupt 1 – Interrupt Active 7.3.
PAGE 47
7.4 Using the Watchdog in an Application The following topics are provided to aid you in learning to use watchdog in an application. 7.4.1 WDT Unlocking and Programming Sequence Unlocking and programming the WDT Memory Mapped registers involves the following sequence: 1. Write “80” to the Reload Register (offset BAR + 0Ch) 2. Write “86” to the Reload Register (offset BAR + 0Ch) 3. Write to desired memory mapped register (offset BAR + 0Xh) 7.4.
PAGE 48
Chapter 8 8 System BIOS The embedded BIOS on the cPB-4612 is implemented as firmware that resides in the on-board flash read-only memory (ROM). The BIOS contains standard PC-compatible basic input/output (I/O) services and several DTI specific functions and features. Support for applicable SBC peripheral devices (SCSI, NIC, video adapters, etc.), that are also loaded into the SBC flash ROM, will not be specified in this document. Hooks are provided to support adding BIOS code for these adapters.
PAGE 49
8.1 BIOS Upgrade and Recovery To reprogram the BIOS or update it if it becomes corrupted, use the DTIFLASH.EXE utility available from DTI and discussed later in this chapter. 8.1.1 Flash Utility Program DTIFLASH.EXE is a utility program that can be obtained from DTI in the event a BIOS should be updated. Run DTIFLASH.EXE to modify the BIOS in the on-board flash memory. DTIFLASH.EXE eliminates the need for a PROM programmer and for removing boards and chips from the system.
PAGE 50
Once the memory is present, the compressed portions of the BIOS are de-compressed into the shadow memory occupying the standard BIOS memory ranges. The BIOS can now scan for and initialize other interfaces such as I/O devices and items on the PCI or ISA busses. If a video adapter is in the system it is located and initialized. The video adapter will sign-on and its manufacturer, chip type, and creation date will appear on the screen.
PAGE 51
devices within a category (such as to boot from IDE hard drive instead of SCSI), or to permanently change the boot order, you will have to enter SETUP and change the boot options. If any errors are detected up to this point they will now be displayed on the screen along with the following prompt to direct further actions. Pressing F1 will ignore the errors and continue with the boot process.
PAGE 52
ROM Utilities SYSTEM SUMMARY Displays various information about the system installed SYSTEM SETUP Used to configure the time/date, floppy drive types, and other BIOS options HARD DISK SETUP Used to configure the hard drive types BOOT ORDER Used to specify boot device ordering PERIPHERALS Used to enable/disable onboard I/O devices USB CONFIG Used to configure USB Legacy Support MISC CONFIG Used to configure PCI, PnP, and ACPI options EVENT LOGGING Used to view and control the system event log
PAGE 53
8.2.3 System Summary The System Configuration Summary utility provides valuable information about the system. The information supplied can also be useful in determining items that are present in the systems and how they are configured. The System Configuration Summary screen is shown below, followed by a brief description of information supplied. SYSTEM CONFIGURATION SUMMARY SYSTEM SUMMARY Diversified Technology, Inc – cPB4612 SYSTEM SETUP CPU Type HARD DISK SETUP BOOT ORDER CPU Speed : 1.
PAGE 54
Build Date: Displays the date on which the BIOS was generated. PCB Revision: Displays the PCB board revision level. Hard Disk 0 - 3: Displays the drive type selected for the IDE drive. COM Ports: Displays the I/O addresses of all installed serial ports. Memory Mode: Displays the type and speed of the memory. PMC Slots: Displays the PCI type and speed of PMC slots. USB Devices: Displays the types of all connected USB devices. 8.2.
PAGE 55
System Time: A new time is set by typing in the HOUR, MINUTE, and SECONDS each followed by pressing < ENTER >. The time is displayed in 24-hour format; therefore, AM hours range from 0 through 11 and the PM hours range from 12 through 23. Invalid times cannot be entered. System Date: A new date is set by tying in the MONTH, DAY, and YEAR each followed by pressing . If one of the parameters is out of range, the new date will not be entered.
PAGE 56
8.2.5 IDE Config The IDE Configuration Utility is used to configure the hard drive controller and interface properties for the system. The following page describes the configuration options.
PAGE 57
8.2.6 Hard Disk Setup The Hard Drive Configuration Utility is used to configure the hard drives installed in the system. The following page describes the configuration options. PRIMARY MASTER CONFIGURATION SUMMARY IDE CONFIG PRIMARY MASTER PRIMARY SLAVE Device : Hard Disk Vendor : SMART ATA FLASH DISK Size : 513MB LBA Mode : Supported SECONDARY MASTER Block Mode: Not Supported PIO Mode : 4 Async DMA : Not Supported SECONDARY SLAVE Ultra DMA : Not Supported S.M.A.R.T.
PAGE 58
Hard Drive Setup Descriptions The configuration options described below work identically for HARD DRIVES 0 - 3. Device: Displays the type of IDE device currently installed. Type choices include Not Installed, Hard Disk, ATAPI CDROM, and ARMD. Vendor: Displays the manufacturer device identification information. Size: Displays the storage capacity of the device. LBA Mode: Displays support for Logical Block Accessing.
PAGE 59
8.2.7 Boot Order The Boot Order Configuration Utility is used to determine the order in which the BIOS will attempt to boot from devices. The BIOS attempts to boot from the devices in descending order beginning from the top of the list. If the device is not bootable, then the next item down in the list is tried. Removable Devices and Hard Disks have further ordering within their category. The following page describes the configuration options.
PAGE 60
Boot Order Descriptions Boot Device Priority: Selects the boot order for installed bootable devices. The BIOS attempts to boot in descending order beginning from the top of the list. ATAPI CDROM Drives: Boot from an IDE CDROM. Hard Disk Devices: Boot from hard disk drive. The desired hard drive must be selected through Hard Disk Drives. Removable Devices: Boot from legacy floppy diskette, removable LS-120, USB, or ZIP drives. The desired removable device must be selected.
PAGE 61
8.2.8 Peripherals The Peripheral Configuration Utility allows onboard devices to be enabled, disabled, or configured. The onboard programmable I/O adapter includes a floppy disk interface, two serial ports, and a parallel printer port.
PAGE 62
Onboard Peripheral Control Descriptions Video Controller: This item displays the enable/disable status of the onboard video controller. Graphics Memory Select: Selects the amount of system memory used by the internal graphics device. The choices are 1MB, 4MB, 8MB, 16MB, or 32MB. Ethernet Controller: This item controls the enable/disable of the 10/100 Ethernet controller. The default is enabled. Ethernet Boot ROM: Controls the embedded Ethernet boot ROM allowing for remote network booting.
PAGE 63
I/O Address Interrupt COM Port 3F8h IRQ4 COM1 2F8h IRQ3 COM2 3E8h IRQ4 COM3 2E8h IRQ3 COM4 8.2.9 USB Configuration The USB Configuration Utility allows control of the board’s USB features. USB CONFIGURATION UTILITY SYSTEM SUMMARY USB DEVICES DETECTED USB Devices : 1 Keyboard, 1 Mouse, 1 Hub, 1 Drive SYSTEM SETUP USB Configuration HARD DISK SETUP USB Function All USB Ports USB 2.0 Controller Enabled USB 2.
PAGE 64
USB Control Descriptions USB Function: Enables USB host controllers. May be enabled for all ports, specific ports, or no ports. USB 2.0 Controller: Controls the USB 2.0 Controller. When enabled, the system will support high-speed (480 Mbps) USB devices, provided the OS loads a driver for the 2.0 Controller. USB 2.0 Controller Mode: Toggles the USB 2.0 Controller between HiSpeed (480Mbps) and FullSpeed (12Mpbs). Legacy USB Support: Controls whether USB devices are available after POST.
PAGE 65
8.2.10 MISC Config The PCI and PNP Configuration Utility allows configuration of the PCI bus, PNP options, as well as ACPI related items. MISC. CONFIGURATION UTILITY SYSTEM SUMMARY PCI OPTIONS SYSTEM SETUP PCI Latency Timer 64 Allocate IRQ to PCI VGA Yes Interrupt 19 Capture Disabled Reserved Memory Size 16k BOOT ORDER Reserved Memory Address D0000 PERIPHERALS PNP OPTIONS HARD DISK SETUP Plug & Play O/S No USB CONFIG Reset Config Data No MISC.
PAGE 66
Reserved Memory Address: This item specifies the location of the Reserved Memory if not disabled. PNP Options Descriptions Plug & Play O/S: If disabled (default), the BIOS will set up any plug & play devices. If enabled, the operating system is assumed to configure plug & play devices. Reset Configuration Data: If set to “Yes”, the plug & play configuration is reset after leaving SETUP. This option is automatically reset to “No”. ACPI / Power Settings ACPI 2.
PAGE 67
8.2.11 Event Logging The Event Logging Configuration Utility is used to configure and view system events that have been logged. EVENT LOGGING CONFIGURATION UTILITY SYSTEM SUMMARY SYSTEM SETUP HARD DISK SETUP View Event Log BOOT ORDER Mark All Events As Read Clear Event Log PERIPHERALS Event Log Statistics USB CONFIG ↑↓ Select Screen Enter Go to Sub Screen F1 General Help Esc Exit MISC.
PAGE 68
8.2.12 Security/Virus The Security and Anti-Virus Configuration Utility is used to set system passwords and control system antivirus items. SECURITY AND ANTI-VIRUS CONFIGURATION UTILITY SYSTEM SUMMARY SYSTEM SETUP HARD DISK SETUP Supervisor Password : Not Installed BOOT ORDER User Password : Not Installed PERIPHERALS Change Supervisor Password Change User Password USB CONFIG Clear User Password MISC.
PAGE 69
8.2.13 Exit The Exit Menu provides a way to exit setup and save or discard changes. It also provides a way to load the default settings stored in the BIOS. EXIT MENU SYSTEM SUMMARY SYSTEM SETUP Save Changes and Exit HARD DISK SETUP Discard Changes and Exit Load Defaults BOOT ORDER Discard Changes PERIPHERALS Save Custom Defaults Load Custom Defaults USB CONFIG Clear Custom Defaults MISC.
PAGE 70
8.3 Plug and Play (PnP) The system BIOS supports the following industry standards for making the system “Plug and Play ready” such as ACPI, PCI local bus specification rev 2.1 and SMBIOS 1. 8.3.1 Resource Allocation The system BIOS identifies, allocates, and initializes resources in a manner consistent with industry standards. The BIOS scans, in order, for the following: ISA devices: Add-in ISA devices are not supported on this platform.
PAGE 71
Drivers and/or the OS can detect the installed devices and determine resource consumption using the defined PCI, legacy PnP BIOS, and/or ACPI BIOS interface functions. 8.3.4 Legacy ISA Configuration Legacy ISA add-in devices are not supported by these platforms. 8.3.
PAGE 72
LEDS Status MSB to LSB Visible colors: FFRF (Off Off Red Off) Bit in the lower nibble is high: POST CODE 02--- BIT values (MSB to LSB) 0000 0010 I I Upper Nibble Lower Nibble LEDS Status MSB to LSB Visible colors: FFGF (Off Off Green Off) Bits in the same location are both high: POST CODE 33 --- BIT values (MSB to LSB) 0011 0011 I I Upper Nibble Lower Nibble LEDS Status MSB to LSB Visible colors: FFOO (Off Off Orange Orange) The following table is provided to show the most important POST CODES: POS
PAGE 73
If the board fails to boot or hangs-up at any of these POST codes, please follow these steps. Step1: Check all power connections and cables to verify they are fully inserted and there are not any loose connections. Step2: Observe the indicating POST code and refer to the following section pertaining to the failure. POST CODES 08 TROUBLE SHOOTING HINT Check the CPU to see if it is fully seated in its socket.
PAGE 74
Appendix A A Specifications This appendix describes the electrical, environmental, and mechanical specifications of the cPB-4612. It includes connector descriptions and pin outs, as well as illustrations of the board dimensions and connector locations. A.1 Electrical and Environmental The topics listed below provide tables and illustrations showing the following electrical and environmental specifications: • Absolute maximum ratings • DC operating characteristics • Battery backup characteristics A.
PAGE 75
Supply Current, Icc: 4.5A average (typical with 1.2 GHz processor and 512 MB SDRAM. Peak (short duration) power supply current may be significantly higher (up to 50%) and will vary depending upon the application. Supply Current, Icc3: 2.5A average (typical with 1.2 GHz processor and 512 MB SDRAM. Peak (short duration) power supply current may be significantly higher (up to 50%) and will vary depending upon the application. Supply Current, AUX + (12V): 50mA maximum A.2.
PAGE 76
A.4.1 Board Dimensions and Weight The cPB-4612 meets the CompactPCI Specification, PICMG 2.0, Version 2.1** for all mechanical parameters. In a CompactPCI enclosure with 0.8 inch spacing. Mechanical dimensions are shown in the "PCB Dimensions" illustration and are outlined below. PCB Dimensions: 233.35 mm x 160 mm x 1.6 mm Board Dimensions: 6U x 4HP (one slot) Weight: 509 grams (18 ounces) w/ processor, heatsink, 512MB memory PCB Dimensions 233.35 mm 160.
PAGE 77
67
PAGE 78
Appendix B B Connectors As shown in the "Connector Locations" figure, the cPB-4612 includes several connectors to interface to application-specific devices. A brief description of each connector is given in the "Connector Assignments" table below. A detailed description and pin out for each connector is given in the following topics.
PAGE 79
B.1 Connector Locations CPB-4612 Connectors Locations (Topside) J4 - USB Port J3 - COM1 Serial Port J1 - 10/100 Ethernet J2 - CompactPCI P5 39 J6 – 66Mhz/64bit PMC site (JN1) 1 J7 – 66Mhz/64bit PMC site (JN2) 3.3V Key P/N:651004612 cPB4612 REV. 1.0 1 J9 – 66Mhz/64bit PMC site (JN3) 1 J10 – 66Mhz/64bit PMC site (JN4) S/N W/O J5 - CPLD Debug Header 38 1 DIVERSIFIED TECHNOLOGY COPYRIGHT 2004MADE IN USA 1 1 U26 - SO-DIMM socket 64 102 128 66Mhz/64bit PMC site 3.
PAGE 80
Backplane Connectors - Pin Locations E D C B A J1 1 11 J2 15 25 J3 1 22 1 19 J5 1 70 E D C B 22 A
PAGE 81
B.2 J15 (CompactPCI Bus Connector) J15 is a 110-pin, 2 mm x 2 mm, female 32-bit CompactPCI connector (AMP 352068-1). Rows 12-14 are used for connector keying. See the "J1 CompactPCI Bus Connector Pin out" table below for pin definitions. Refer to the "Backplane Connectors – Pin Locations" illustration for pin placement.
PAGE 82
B.3 J11 (CompactPCI Bus Connector) J11 is a 110-pin 2 mm x 2 mm female 64-bit CompactPCI connector (AMP 352152-1). See the "J11 CompactPCI Bus Connector Pin out" table for pin definitions and the "Backplane Connectors - Pin Locations" illustration for pin placement.
PAGE 83
B.4 J8 (CompactPCI Connector) J8 is a 95-pin 2 mm x 2 mm female connector (AMP 352171-1). See the "J8 Connector Pin out" table below for pin definitions and the "Backplane Connectors - Pin Locations" illustration for pin placement.
PAGE 84
B.5 J2 (Rear Panel I/O CompactPCI Connector) J2 is a 110-pin 2 mm x 2 mm female connector (AMP 352152-1) providing rear-panel user I/O. See the "J2 Rear Panel I/O Connector Pin out" table below for pin definitions and the "Backplane Connectors - Pin Locations" illustration for pin placement.
PAGE 85
B.6 J1 (10/100 Ethernet) J1 is an 8-pin RJ-45 connector providing 10 Mb (10BASE-T) and 100 Mb (100BASE-TX) protocols out the front of the board. Two LEDs are located inside each RJ-45 connector: First LED: • Green indicates a link • Blinking Green indicates activity Second LED: • Off = 10 MB • Green = 100 MB Ethernet signals are directed out the front J1 port. B.7 J4 (Universal Serial Bus 0 connector) J4 (Port0) is a Universal Serial Bus (USB) Interface connector .
PAGE 86
B.8 J3 (COM1 Serial Port) J3 is an DB9 connector providing a front-panel COM1 interface. See the "J3 COM1 Serial Port Pin out" table below for pin definitions. J3 COM1 Serial Port Pin out Pin# Function Pin# Function 1 DCD 6 DSR 2 RXD 7 RTS 3 TXD 8 CTS 4 DTR 9 RI 5 GND - SCD B.9 J6, J7, J9, J10 (64bit/66Mhz PCI Mezzanine Connectors) J6, J7, J9, and J10 are 64-pin, 1.00mm, dual row, vertical stacking receptacles providing a PCI local bus interface to optional PMC cards.
PAGE 87
24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND GND CBE(3)# PCI_AD(22) PCI_AD(21) PCI_AD(19) VCC VCC3 (VIO) PCI_AD(17) 56 57 58 59 60 61 62 63 64 GND VCC3 (VIO) PCI_AD(3) PCI_AD(2) PCI_AD(1) PCI_AD(0) VCC GND REQ64# J7 – 66Mhz/64bit PMC site (JN2) +12V 33 GND PMC_TRST_64_66# 34 PMC_RSVD34 PMC_TMS_64_66 35 TRDY# NC 36 VCC3 PMC_TDI_64_66 37 GND GND 38 STOP# GND 39 PERR# NC 40 GND NC 41 VCC3 NC 42 SERR# BUSMODE2# 43 CBE(1)# VCC3 44 GND
PAGE 88
J9 – 66Mhz/64bit PMC site (JN3) 1 NC 33 GND 2 NC 34 PCI_AD(48) 3 GND 35 PCI_AD(47) 4 CBE(7)# 36 PCI_AD(46) 5 CBE(6)# 37 PCI_AD(45) 6 CBE(5)# 38 GND 7 CBE(4)# 39 VCC3 (VIO) 8 GND 40 PCI_AD(44) 9 VCC3 (VIO) 41 PCI_AD(43) 10 PAR64 42 PCI_AD(42) 11 PCI_AD(63) 43 PCI_AD(41) 12 PCI_AD(62) 44 GND 13 PCI_AD(61) 45 GND 14 GND 46 PCI_AD(40) 15 GND 47 PCI_AD(39) 16 PCI_AD(60) 48 PCI_AD(38) 17 PCI_AD(59) 49 PCI_AD(37) 18 PCI_AD(58) 50 GND 19 PCI_A
PAGE 89
J10 – 66Mhz/64bit PMC site (JN4) 1 PIM[1] 33 PIM[33] 2 PIM[2] 34 PIM[34] 3 PIM[3] 35 PIM[35] 4 PIM[4] 36 PIM[36] 5 PIM[5] 37 PIM[37] 6 PIM[6] 38 PIM[38] 7 PIM[7] 39 PIM[39] 8 PIM[8] 40 PIM[40] 9 PIM[9] 41 PIM[41] 10 PIM[10] 42 PIM[42] 11 PIM[11] 43 PIM[43] 12 PIM[12] 44 PIM[44] 13 PIM[13] 45 PIM[45] 14 PIM[14] 46 PIM[46] 15 PIM[15] 47 PIM[47] 16 PIM[16] 48 PIM[48] 17 PIM[17] 49 PIM[49] 18 PIM[18] 50 PIM[50] 19 PIM[19] 51 PIM[51] 20
PAGE 90
B.10 J12 and J13 (32bit/33Mhz PCI Mezzanine Connectors) J12 and J13 are 64-pin, 1.00mm, dual row, vertical stacking receptacles providing a PCI local bus interface to optional PMC cards. These connectors provide a complete 32-bit PCI interface. See the following "J12 PCI Mezzanine Connector Pin out" and "J13 PCI Mezzanine Connector Pin out" tables for pin definitions.
PAGE 91
J13 – 33Mhz/32bit PMC site (JN2) 1 +12V 33 GND 2 PMC_TRST_32_33# 34 NC 3 PMC_TMS_32_33 35 TRDY# 4 NC 36 VCC3 5 PMC_TDI_32_33 37 GND 6 GND 38 STOP# 7 GND 39 PERR# 8 NC 40 GND 9 NC 41 VCC3 10 NC 42 SERR# 11 BUSMODE2# 43 CBE(1)# 12 VCC3 44 GND 13 PCIRST# 45 PCI_AD(14) 14 BUSMODE3# 46 PCI_AD(13) 15 VCC3 47 GND 16 BUSMODE4# 48 PCI_AD(10) 17 PME# 49 PCI_AD(8) 18 GND 50 VCC3 19 PCI_AD(30) 51 PCI_AD(7) 20 PCI_AD(29) 52 NC 21 GND 53 V
PAGE 92
B.11 J14 (IDE Connector) J14 is a 50-pin, header providing a primary IDE channel interface. See the "J14 IDE Connector Pin out" table below for pin definitions. J14 – 2.
PAGE 93
83
PAGE 94
Appendix C C Thermal Considerations This appendix describes the thermal requirements for reliable operation of a cPB-4612 using the Mobile Pentium 4 processor - M. It covers basic thermal requirements and provides specifics about monitoring the board and processor temperature.
PAGE 95
C.1 Thermal Requirements The cPB-4612 is equipped with an integrated heatsink for cooling the processor module. The maximum processor core temperature must not exceed 100°C. The heatsink allows a maximum ambient air temperature of 50°C with 200 linear feet per minute (LFM) of airflow. The maximum power dissipation of the CPU is 25 W at 1.2 GHz and 1.20V. CAUTION: External airflow must be provided at all times during operation to avoid damaging the CPU.
PAGE 96
When checking airflow conditions, let the Processor Core Temperature Test dwell for at least 30 minutes and verify that the core temperature does not exceed 65°C. The processor "core" temperature must never exceed 100°C under any condition of ambient temperature or usage. WARNING: Temperatures over 100°C may result in permanent damage to the processor. Refer to the "Thermal Requirements" table for more information.
PAGE 97
87
PAGE 98
Appendix D D Datasheet Reference This appendix provides links to datasheets, standards, and specifications for the technology designed into the cPB-4612.
PAGE 99
D.1 CompactPCI CompactPCI specifications can be purchased from the PCI Industrial Computer Manufacturers Group (PICMG) for a nominal fee. A short form CompactPCI specification is also available on PICMG's Website at: http://www.picmg.org** D.2 Ethernet Refer to the Intel 82559 Fast Ethernet PCI Controller datasheet for more information on the Ethernet 10/100 LAN Controller. The datasheet is available from Intel's Website at: http://developer.intel.com/design/network/products/lan/controllers/82559.
PAGE 100
D.5 PMC Specification For more information about PMC modules and the PMC Specification, refer to the sponsoring organization's Website at: http://www.vita.com/** D.6 Super I/O Refer to the SMSC LPC47M192 Super I/O with Hardware Monitoring Block datasheet for more information on the following cPB-4612 functions: • Hardware Monitoring The datasheet is available online from the SMSC Website at: http://www.smsc.
PAGE 101
91
PAGE 102
Appendix E E Agency Approvals E.1 CE Certification The cPB-4612 meets the intent of Directive 89/336/EEC for Electromagnetic Compatibility [EN55024:1998, EN55022:1998] and Low-Voltage Directive 73/23/EEC for Product Safety [EN609501:2001]. The final product configuration may need further testing. DTI is ready to work with you to get your product through the CE certification process E.
PAGE 103
approved chassis. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This product generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
PAGE 104
Appendix F F cRT Specifications The cRT-4612 hosts a CompactFlash site and a 40 pin IDE connector, and provides access to the following features on the rear panel: • Two USB 2.0 Ports • Serial Communications on COM2 • Video via standard CRT connector • A PIM site that can be used in conjunction with a PMC card, on the cPB-4612, to provide additional I/O to the rear panel.