87C196CB Supplement to 8XC196NT User’s Manual
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CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 RELATED DOCUMENTS .............................................................................................. 1-2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2.1 DEVICE FEATURES ..................................................................................................... 2-1 2.2 BLOCK DIAGRAM .................................................
87C196CB SUPPLEMENT 7.4.4 Programming a Message Acceptance Filter ...........................................................7-17 7.5 CONFIGURING MESSAGE OBJECTS ....................................................................... 7-20 7.5.1 Specifying a Message Object’s Configuration .........................................................7-21 7.5.2 Programming the Message Object Identifier ...........................................................7-22 7.5.
CONTENTS FIGURES Figure 2-1 2-2 2-3 2-4 4-1 4-2 5-1 5-2 5-3 5-4 5-5 6-1 6-2 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 8-1 9-1 9-2 10-1 A-1 Page 87C196CB Block Diagram............................................................................................2-2 Clock Circuitry ..............................................................................................................2-3 Internal Clock Phases .................
8XC196CB SUPPLEMENT FIGURES Figure Page A-2 87C196CB 100-pin QFP Package ..............................................................................
CONTENTS TABLES Table 1-1 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 4-1 5-1 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 9-1 10-1 10-2 10-3 10-4 A-1 A-2 A-3 A-4 A-5 Page Related Documents ......................................................................................................1-2 Features of the 8XC196NT and 87C196CB .................................................................2-1 State Times at Various Frequencies ................................................
1 Guide to This Manual
CHAPTER 1 GUIDE TO THIS MANUAL This document is a supplement to the 8XC196NT Microcontroller User’s Manual. It describes the differences between the 87C196CB and the 8XC196NT. For information not found in this supplement, please consult the 8XC196NT Microcontroller User’s Manual (order number 272317) or the 87C196CB datasheet (87C196CA/87C196CB 20 MHz Advanced 16-Bit CHMOS Microcontroller with Integrated CAN 2.0, order number 272405). 1.
87C196CB SUPPLEMENT Chapter 9 — Interfacing with External Memory — discusses differences in the bus timing modes supported by the 8XC196NT and the 87C196CB. Chapter 10 — Programming the Nonvolatile Memory — describes the memory maps and recommended circuits to support programming of the 87C196CB’s 56 Kbytes of OTPROM. Appendix A — Signal Descriptions — describes the additional signals implemented on the 87C196CB. Glossary — defines terms with special meaning used throughout this supplement.
2 Architectural Overview
CHAPTER 2 ARCHITECTURAL OVERVIEW This chapter describes architectural differences between the 87C196CB and the 8XC196NT. Both the 8XC196NT and the 87C196CB are designed for high-speed calculations and fast I/O. With the addition of the CAN (controller area network) peripheral, the 87C196CB reduces pointto-point wiring requirements, making it well-suited to automotive and factory automation applications. The 87C196CB is available in either an 84-pin or a 100-pin package.
87C196CB SUPPLEMENT 2.2 BLOCK DIAGRAM Figure 2-1 shows the major blocks within the device. The 8XC196NT and 87C196CB have the same peripheral set with the exception of the CAN (controller area network) peripheral, which is unique to the 87C196CB. The CAN peripheral manages communications between multiple network nodes. This integrated peripheral is similar to Intel’s standalone 82527 CAN serial communications controller, supporting both the standard and extended message frames specified by the CAN 2.
ARCHITECTURAL OVERVIEW Disable PLL (Powerdown) FXTAL1 Phase Comparator FXTAL1 XTAL1 Disable Oscillator (Powerdown) Phaselocked Oscillator 4FXTAL1 XTAL2 Disable Clock Input (Powerdown) f PLLEN Filter Phase-locked Loop Clock Multiplier Divide-by-two Circuit f 2 Disable Clocks (Powerdown) Peripheral Clocks (PH1, PH2) Clock Generators CLKOUT CPU Clocks (PH1, PH2) Disable Clocks (Idle, Powerdown) A3168-01 Figure 2-2.
87C196CB SUPPLEMENT XTAL1 t t 1 State Time 1 State Time PH1 PH2 CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0805-01 Figure 2-3. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. Table 2-2.
ARCHITECTURAL OVERVIEW PLLEN = 0 XTAL1 (5 MHz) t = 80ns f TXHCH CLKOUT PLLEN = 1 XTAL1 (5 MHz) t = 20ns f TXHCH CLKOUT A3170-01 Figure 2-4. Effect of Clock Mode on CLKOUT Frequency Table 2-3.
3 Memory Partitions
CHAPTER 3 MEMORY PARTITIONS This chapter describes the differences in the address space of the 87C196CB from that of the 8XC196NT. The 87C196CB has 56 Kbytes of one-time-programmable read-only memory (OTPROM), while the 8XC196NT is available with 32 Kbytes. The 87C196CB also has an additional 512 bytes of register RAM. The 87C196CB is available in either an 84-pin or a 100-pin package.
87C196CB SUPPLEMENT Table 3-2.
MEMORY PARTITIONS Table 3-3.
87C196CB SUPPLEMENT Table 3-4.
MEMORY PARTITIONS Table 3-4.
87C196CB SUPPLEMENT Table 3-5.
MEMORY PARTITIONS Table 3-6.
87C196CB SUPPLEMENT 3-8
MEMORY PARTITIONS Table 3-7.
87C196CB SUPPLEMENT Table 3-8.
MEMORY PARTITIONS Table 3-8.
87C196CB SUPPLEMENT Table 3-9.
MEMORY PARTITIONS Table 3-9.
87C196CB SUPPLEMENT Table 3-9.
MEMORY PARTITIONS Table 3-9.
87C196CB SUPPLEMENT Table 3-9.
MEMORY PARTITIONS Table 3-9.
87C196CB SUPPLEMENT Table 3-9.
MEMORY PARTITIONS Table 3-9.
Table 3-9.
4 Standard and PTS Interrupts
CHAPTER 4 STANDARD AND PTS INTERRUPTS 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES The interrupt structure of the 87C196CB is the same as that of the 8XC196NT. The only difference is that INT13, which was reserved on the 8XC196NT, supports the CAN peripheral. Table 4-1 lists the 87C196CB’s interrupts sources, default priorities (30 is highest and 0 is lowest), and vector addresses. Figures 4-1 and 4-2 illustrate the interrupt mask and pending registers. Table 4-1.
87C196CB SUPPLEMENT Address: Reset State: INT_MASK1 0013H 00H The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it. 7 0 NMI 7:0 EXTINT CAN RI TI SSIO1 SSIO0 CBF Setting a bit enables the corresponding interrupt.
5 I/O Ports
CHAPTER 5 I/O PORTS 5.1 PORT 0 AND EPORT The I/O ports of the 87C196CB are functionally identically to those of the 8XC196NT. However, the 87C196CB implements all eight pins of port 0, and the 100-pin 87C196CB also implements all eight pins of the EPORT. The associated registers have been modified to include bits corresponding to the upper nibble of the ports. Table 5-1 provides an overview of the 8XC196CB’s I/O ports.
87C196CB SUPPLEMENT Address: Reset State: EP_DIR 1FE3H FFH In I/O mode, each bit of the extended port I/O direction (EP_DIR) register controls the direction of the corresponding pin. Clearing a bit configures a pin as a complementary output; setting a bit configures a pin as either an input or an open-drain output. (Open-drain outputs require external pull-ups).
I/O PORTS Address: Reset State: EP_PIN 1FE7H XXH Each bit of the extended port input (EP_PIN) register reflects the current state of the corresponding pin, regardless of the pin configuration. 7 0 PIN7 Bit Number 7:0 PIN6 PIN5 PIN4 PIN3 Bit Mnemonic PIN2 PIN1 PIN0 Function Extended Address Port Pin x Input PIN7:0 This bit contains the current state of EPORT.x. Figure 5-4.
6 Analog-to-digital (A/D) Converter
CHAPTER 6 ANALOG-TO-DIGITAL (A/D) CONVERTER 6.1 ADDITIONAL A/D INPUT CHANNELS The 87C196CB’s A/D converter is functionally identical to that of the 8XC196NT, but it has eight analog input channels instead of four. Table 6-1 lists the A/D signals. Figure 6-1 describes the command register and Figure 6-2 describes the result register. Table 6-1. A/D Converter Pins Port Pin A/D Signal A/D Signal Type P0.7:0 ACH7:0 I — ANGND GND Description Analog inputs.
87C196CB SUPPLEMENT Address: Reset State: AD_COMMAND 1FACH C0H The A/D command (AD_COMMAND) register selects the A/D channel number to be converted, controls whether the A/D converter starts immediately or with an EPA command, and selects the conversion mode. 7 0 — Bit Number — M1 M0 GO Bit Mnemonic ACH2 ACH1 ACH0 Function 7:6 — Reserved; for compatibility with future devices, write zeros to these bits. 5:4 M1:0 A/D Mode† These bits determine the A/D mode.
ANALOG-TO-DIGITAL (A/D) CONVERTER Address: Reset State: AD_RESULT (Read) 1FAAH 7F80H The A/D result (AD_RESULT) register consists of two bytes. The high byte contains the eight mostsignificant bits from the A/D converter. The low byte contains the two least-significant bits from a tenbit A/D conversion, indicates the A/D channel number that was used for the conversion, and indicates whether a conversion is currently in progress.
7 CAN Serial Communications Controller
CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER The 87C196CB has a peripheral not found in the 8XC196NT — the CAN (controller area network) peripheral. The CAN serial communications controller manages communications between multiple network nodes. This integrated peripheral is similar to Intel’s standalone 82527 CAN serial communications controller. It supports both the standard and the extended message frames specified by CAN 2.0 protocol parts A and B developed by Robert Bosch, GmbH.
87C196CB SUPPLEMENT This bus configuration reduces point-to-point wiring requirements, making the CAN controller well suited to automotive and factory automation applications. In addition, it relieves the CPU of much of the communications burden while providing a high level of data integrity through error management logic. The CAN controller (Figure 7-2) has one input pin, one output pin, control and status registers, and error detection and management logic.
CAN SERIAL COMMUNICATIONS CONTROLLER 7.2 CAN CONTROLLER SIGNALS AND REGISTERS Table 7-1 describes the CAN controller’s pins, and Table 7-2 describes the control and status registers. Table 7-1. CAN Controller Signals Signal Type RXCAN I Description Receive This signal carries messages from other nodes on the CAN bus to the CAN controller. TXCAN O Transmit This signal carries messages from the CAN controller to other nodes on the CAN bus. Table 7-2.
87C196CB SUPPLEMENT Table 7-2. Control and Status Registers (Continued) Register Mnemonic †† CAN_MSGxCON1 Register Address †† 1Ey1H Description Message Object x Control 1 Program this register to indicate that a message is ready to transmit or to initiate a transmission. Read this register to determine whether the message object contains new data, whether a message has been overwritten, whether software is updating the message, and whether a transfer is pending.
CAN SERIAL COMMUNICATIONS CONTROLLER 7.3.1 Address Map The CAN controller has 256 bytes of RAM, containing 15 message objects and control and status registers at fixed addresses. Each message object occupies 15 consecutive bytes beginning at a base address that is a multiple of 16 bytes. The byte above each message object is reserved (indicated by a dash (—) character) or occupied by a control register. The lowest 16 bytes of RAM contain the remaining control and status registers (Table 7-3).
87C196CB SUPPLEMENT Table 7-4. Message Object Structure Hex Address† 1Ex7–1ExE Data Bytes 0–7 1Ex6 Message Configuration 1Ex2–1Ex5 Message Identifier 0–3 1Ex0–1Ex1 Message Control 0–1 † 7.3.2.1 Contents x = message object number, in hexadecimal Receive and Transmit Priorities The lowest-numbered message object always has the highest priority, regardless of the message identifier.
CAN SERIAL COMMUNICATIONS CONTROLLER Table 7-5. Effect of Masking on Message Identifiers 7.3.3 Transmit message object ID 11000000000 Mask (0 = don’t care; 1 = must match) 00000000011 Received remote message object ID 00111111100 Resulting message object ID 00111111100 Message Frames A message object is contained within a message frame that adds control and error-detection bits to the content of the message object.
87C196CB SUPPLEMENT Table 7-6. Standard Message Frame Field SOF Description Start-of-frame. A dominant (0) bit marks the beginning of a message frame. Bit Count 1 11-bit message identifier. Arbitration RTR. Remote transmission request. Dominant (0) for data frames; recessive (1) for remote frames. 12 IDE. Identifier extension bit; always dominant (0). Control r0. Reserved bit; always dominant (0). 6 Data Data. 1 to 8 bytes for data frames; 0 bytes for remote frames. CRC CRC code.
CAN SERIAL COMMUNICATIONS CONTROLLER 7.3.4 Error Detection and Management Logic The CAN controller has several error detection mechanisms, including cyclical redundancy checking (CRC) and bit coding rules (stuffing and destuffing). The CAN controller generates a CRC code for transmitted messages and checks the CRC code of incoming messages. The CRC polynomial has been optimized for control applications with short messages.
87C196CB SUPPLEMENT 7.3.5 Bit Timing A message object consists of a series of bits transmitted in consecutive bit times. The CAN protocol specifies a bit time composed of four separate, nonoverlapping time segments: a synchronization delay segment, a propagation delay segment, and two phase delay segments (Figure 7-4 and Table 7-8). The CAN controller implements a bit time as three segments, combining PROP_SEG and PHASE_SEG1 into tTSEG1 (Figure 7-5 and Table 7-9).
CAN SERIAL COMMUNICATIONS CONTROLLER Bit Time t SYNC t TSEG1 t TSEG2 _SEG 1 tq (TSEG2 + 1)tq (TSEG1 + 1)tq Sample Transmit A2602-01 Figure 7-5. A Bit Time as Implemented in the CAN Controller Table 7-9. CAN Controller Bit Time Segments Symbol Definition tSYNC_SEG This time segment is equivalent to SYNC_SEG in the CAN protocol. Its length is one time quantum. tTSEG1 This time segment is equivalent to the sum of PROP_SEG and PHASE_SEG1 in the CAN protocol.
87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations The bit timing equations of the integrated CAN controller are equivalent to those for the 82527 CAN peripheral with the DSC bit in the CPU interface register set (system clock divided by two). The following equations show the timing calculations for the integrated CAN controller and the 82527 CAN peripheral, respectively.
CAN SERIAL COMMUNICATIONS CONTROLLER 7.4 CONFIGURING THE CAN CONTROLLER This section explains how to configure the CAN controller. Several registers combine to control the configuration: the CAN control register, the two bit timing registers, and the three mask registers. 7.4.
87C196CB SUPPLEMENT Address: Reset State: CAN_CON (Continued) (87C196CB) 1E00H 01H Program the CAN control (CAN_CON) register to control write access to the bit timing registers, to enable and disable CAN interrupts, and to control access to the CAN bus. 7 87C196CB Bit Number 1 0 — CCE — — Bit Mnemonic IE EIE SIE IE INIT Function Interrupt Enable This bit globally enables and disables interrupts (error, status-change, and message object transmit and receive interrupts).
CAN SERIAL COMMUNICATIONS CONTROLLER 7.4.2 Programming the Bit Timing 0 (CAN_BTIME0) Register Bit timing register 0 (Figure 7-7) defines the length of one time quantum and the maximum amount by which the sample point can be moved (tTSEG1 or tTSEG2 can be shortened and the other lengthened) to compensate for resynchronization.
87C196CB SUPPLEMENT 7.4.3 Programming the Bit Timing 1 (CAN_BTIME1) Register Bit timing register 1 (Figure 7-8) controls the time at which the bus is sampled and the number of samples taken. In single-sample mode, the bus is sampled once and the value of that sample is considered valid. In three-sample mode, the bus is sampled three times and the value of the majority of those samples is considered valid.
CAN SERIAL COMMUNICATIONS CONTROLLER Table 7-11. Bit Timing Requirements for Synchronization Bit Time Segment tTSEG1 tTSEG2 7.4.
87C196CB SUPPLEMENT CAN_SGMSK (87C196CB) Address: Reset State: 1E07H, 1E06H Unchanged Program the CAN standard global mask (CAN_SGMSK) register to mask (“don’t care”) specific message identifier bits for standard message objects. 15 MSK20 87C196CB 8 MSK19 MSK18 — — — — — 7 MSK28 Bit Number 15:13 0 MSK27 Bit Mnemonic MSK20:18 MSK26 MSK25 MSK24 MSK23 MSK22 MSK21 Function ID Mask These bits individually mask incoming message identifier (ID) bits.
CAN SERIAL COMMUNICATIONS CONTROLLER CAN_EGMSK (87C196CB) Address: 1E0BH, 1E0AH, 1E09H, 1E08H Unchanged Reset State: Program the CAN extended global mask (CAN_EGMSK) register to mask (“don’t care”) specific message identifier bits for extended message objects.
87C196CB SUPPLEMENT CAN_MSK15 † (87C196CB) Address: 1E0FH, 1E0EH, 1E0DH, 1E0CH Unchanged Reset State: Program the CAN message 15 mask (CAN_MSK15) register to mask (“don’t care”) specific message identifier bits for message 15 in addition to those bits masked by a global mask (CAN_EGMSK or CAN_SGMSK).
CAN SERIAL COMMUNICATIONS CONTROLLER 7.5.1 Specifying a Message Object’s Configuration Each message object configuration register (Figure 7-12) specifies a message identifier type (standard or extended), transfer direction (transmit or receive), and data length (in bytes).
87C196CB SUPPLEMENT 7.5.2 Programming the Message Object Identifier Each message identifier register (Figure 7-13) specifies the message’s identifier. For messages with extended identifiers, write the identifier to bits ID28:0. For messages with standard identifiers, write the identifier to bits ID28:18. Software can change the identifier during normal operation without requiring a subsequent device reset.
CAN SERIAL COMMUNICATIONS CONTROLLER 7.5.3 Programming the Message Object Control Registers Each message object control register consists of four bit pairs — one bit of each pair is in true form and one is in complement form. This format allows software to set or clear any bit with a single write operation, without affecting the remaining bits. Table 7-12 shows how to interpret the bit-pair values. Table 7-12. Control Register Bit-pair Interpretation Access Type Write Read 7.5.3.
87C196CB SUPPLEMENT CAN_MSGxCON0 x = 1–15 (87C196CB) 1Ex0H (x = 1–F) Unchanged Address: Reset State: Program the CAN message object x control 0 (CAN_MSGxCON0) register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending.
CAN SERIAL COMMUNICATIONS CONTROLLER CAN_MSGxCON0 (Continued) x = 1–15 (87C196CB) 1Ex0H (x = 1–F) Unchanged Address: Reset State: Program the CAN message object x control 0 (CAN_MSGxCON0) register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending.
C196CB SUPPLEMENT CAN_MSGxCON1 x = 1–15 (87C196CB) Address: Reset State: 1Ex1H (x = 1–F) Unchanged The CAN message object x control 1 (CAN_MSGxCON1) register indicates whether a message object has been updated, whether a message has been overwritten, whether the CPU is updating the message, and whether a transmission or reception is pending. This register consists of four bit-pairs — the most-significant bit of each pair is in true form and the least-significant bit is in complement form.
CAN SERIAL COMMUNICATIONS CONTROLLER CAN_MSGxCON1 (Continued) x = 1–15 (87C196CB) Address: Reset State: 1Ex1H (x = 1–F) Unchanged The CAN message object x control 1 (CAN_MSGxCON1) register indicates whether a message object has been updated, whether a message has been overwritten, whether the CPU is updating the message, and whether a transmission or reception is pending.
87C196CB SUPPLEMENT CAN_MSGxDATA0–7 x = 1–15 (87C196CB) Address: Reset State: 1ExEH, 1ExDH, 1ExCH, 1ExBH, 1ExAH, 1Ex9H, 1Ex8H, 1Ex7H (x = 1–F) Unchanged The CAN message object data (CAN_MSGxDATA0–7) registers contain data to be transmitted or data received. Any unused data bytes have random values that change during operation.
CAN SERIAL COMMUNICATIONS CONTROLLER 7.6 ENABLING THE CAN INTERRUPTS The CAN controller has a single interrupt input (INT13) to the interrupt controller. (Generally, PTS interrupt service is not useful for the CAN controller because the PTS cannot readily determine the source of the CAN controller’s multiplexed interrupts.
87C196CB SUPPLEMENT Address: Reset State: CAN_CON (Continued) (87C196CB) 1E00H 01H Program the CAN control (CAN_CON) register to control write access to the bit timing registers, to enable and disable CAN interrupts, and to control access to the CAN bus. 7 — 87C196CB Bit Number 1 0 CCE — — Bit Mnemonic IE EIE SIE IE INIT Function Interrupt Enable This bit globally enables and disables interrupts (error, status-change, and message object transmit and receive interrupts).
CAN SERIAL COMMUNICATIONS CONTROLLER CAN_MSGxCON0 x = 1–15 (87C196CB) 1Ex0H (x = 1–F) Unchanged Address: Reset State: Program the CAN message object x control 0 (CAN_MSGxCON0) register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending.
87C196CB SUPPLEMENT 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS A successful reception or transmission or a change in the status register can cause the CAN controller to generate an interrupt request. The INT_PEND1 register (see Table 7-2 on page 7-3) indicates whether a CAN interrupt request is pending. The CAN interrupt pending register (Figure 7-19) indicates the source of the request (either the status register or a specific message object).
CAN SERIAL COMMUNICATIONS CONTROLLER Address: Reset State: CAN_STAT (87C196CB) 1E01H XXH The CAN status (CAN_STAT) register reflects the current status of the CAN peripheral. 7 Bit Number 7 0 BUSOFF 87C196CB WARN — RXOK Bit Mnemonic BUSOFF TXOK LEC2 LEC1 LEC0 Function Bus-off Status The CAN peripheral sets this read-only bit to indicate that it has isolated itself from the CAN bus (floated the TX pin) because an error counter has reached 256.
87C196CB SUPPLEMENT . CAN_MSGxCON0 (n = 1–15) Address: Reset State: 1Ex0H (x=1–F) Unchanged Program the CAN message object x control 0 register (CAN_MSGxCON0) to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The most-significant bit-pair indicates whether an interrupt is pending.
CAN SERIAL COMMUNICATIONS CONTROLLER 7.8 FLOW DIAGRAMS The flow diagrams in this section describe the steps that your software (shown as CPU) and the CAN controller execute to receive and transmit messages. Table 7-13 lists the register bits shown in the diagrams along with their associated registers and a cross-reference to the figure that describes them. Table 7-13.
87C196CB SUPPLEMENT (All bits undefined) Power Up Initialization MSGVAL INT_PND TXIE RXIE := 1 := 0 := (Application specific) := (Application specific) NEWDAT RMTPND TX_REQ MSGLST := 0 := 0 := 0 := 0 DLC DIR XTD ID := (don't care) := 0 (receive) := (Application specific) := (Application specific) NEWDAT := 0 Process message contents. Process Yes NEWDAT = 1? Restart Process No No Request update? Yes TX_REQ := 1 A2594-01 Figure 7-22.
CAN SERIAL COMMUNICATIONS CONTROLLER (All bits undefined) Power Up MSGVAL := 1 INT_PND := 0 RXIE := (Application specific) Initialization NEWDAT := 0 RMTPND := 0 MSGLST := 0 DIR XTD := 0 (receive) := (Application specific) ID MASK := (Application specific) := (Application specific) Process message contents. INT_PND := 0 NEWDAT := 0 and RMTPND := 0 Process Yes NEWDAT = 1? Restart Process No A2597-02 Figure 7-23.
87C196CB SUPPLEMENT Bus idle? No Yes No TX_REQ=1? MSGLST=0? No Received frame with same identifer as this message object? Yes Yes NEWDAT := 0 Load identifer and control into buffer NEWDAT = 1? Send remote frame MSGLST := 1 No Transmission successful? Store message NEWDAT := 1 TX_REQ := 0 RMTPND := 0 Yes TX_REQ := 0 RMTPND:= 0 No RXIE = 1? No TXIE = 1? Yes Yes INT_PND := 1 INT_PND := 1 A2598-01 Figure 7-24.
CAN SERIAL COMMUNICATIONS CONTROLLER (All bits undefined) Power Up Initialization MSGVAL INT_PND TXIE RXIE := 1 := 0 := (Application specific) := (Application specific) NEWDAT RMTPND TX_REQ MSGLST := 0 := 0 := 0 := 0 DLC DIR XTD := (Application specific) := 1 (transmit) := (Application specific) ID := (Application specific) CPUUPD := 1 NEWDAT := 1 Write/calculate message contents. Update CPUUPD := 0 Want to send? Yes TX_REQ := 1 No Yes Update message? A2596-01 Figure 7-25.
87C196CB SUPPLEMENT Bus free? No Yes No TX_REQ= 1? CPUUPD= 0? No Received remote frame with same identifer as this message object? Yes NEWDAT := 0 Load message into buffer Yes TX_REQ := 1 RMTPND := 1 Send message No RXIE = 1? Transmission successful? Yes INT_PND := 1 Yes No NEWDAT = 1? No TX_REQ := 0 RMTPND := 0 Yes No TXIE = 1? Yes INT_PND := 1 A2595-02 Figure 7-26.
CAN SERIAL COMMUNICATIONS CONTROLLER 7.9 DESIGN CONSIDERATIONS This section outlines design considerations for the CAN controller. 7.9.1 Hardware Reset A hardware reset clears the error management counters and the bus-off state and leaves the registers with the values listed in Table 7-14. Table 7-14. Register Values Following Reset Register 7.9.
87C196CB SUPPLEMENT The CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states (128 occurrences of 11 consecutive recessive bits) before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC2:0 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state.
8 Special Operating Modes
CHAPTER 8 SPECIAL OPERATING MODES 8.1 CLOCK CIRCUITRY The 87C196CB’s idle, powerdown, and ONCE modes are the same as those of the 8XC196NT. The only difference is in the way that the power saving modes disable the clock circuitry (Figure 8-1).
9 Interfacing with External Memory
CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY The 87C196CB’s external memory interface is similar to that of the 8XC196NT. However, the 87C196CB supports only two of the bus timing modes, modes 3 and 0. In addition, the 100-pin 87C196CB has four additional address pins (A23:20). 9.1 ADDRESS PINS The 100-pin 87C196CB has 24 available address pins, A23:16 and AD15:0. The A23:20 timings are identical to those of A19:16. During the CCB fetch, the 100-pin 87C196CB strongly drives 0FFH on A23:16.
87C196CB SUPPLEMENT t MODE 3 CLKOUT ALE RD# TRLDV = 1t AD15:0 Data Address Data TRHDZ = 1t Address Data Address TAVDV = 3t MODE 0 ALE Data RD# TRLDV = 3t AD15:0 Data Address TRHDZ = 1t Data Address Data TAVDV = 5t A0809-01 Figure 9-1.
INTERFACING WITH EXTERNAL MEMORY no direct access† CCR1 The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. Another bit controls whether CCR2 is loaded. 7 0 MSEL1 MSEL0 Bit Number Bit Mnemonic 7:6 MSEL1:0 0 1 WDE BW1 IRC2 LDCCB2 Function External Access Timing Mode Select These bits control the bus-timing modes.
87C196CB SUPPLEMENT no direct access† CCR1 (Continued) The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. Another bit controls whether CCR2 is loaded. 7 1 0 MSEL1 MSEL0 Bit Number Bit Mnemonic IRC2 0 1 WDE BW1 IRC2 LDCCB2 Function Ready Control This bit, along with IRC0 (CCR0.4) and IRC1 (CCR0.
10 Programming the Nonvolatile Memory
CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY The 87C196CB has 56 Kbytes of OTPROM (FF2000–FFFFFFH), while the 8XC196NT has only 32 Kbytes (FF2000–FF9FFFH). The 87C196CB’s programming signals, registers, and procedures are the same as those of the 8XC196NT. This chapter describes the differences in memory mapping and programming circuits for the 87C196CB. 10.
87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory Map Description Address OTPROM Comments FF2000–FFFFFFH OTPROM Cells OFD 0778H OTPROM Cell DED† 0758H UPROM Cell DEI† 0718H UPROM Cell PCCB 0218H Test EPROM Programming VCC 0072H Read Only Programming VPP 0073H Read Only Signature word 0070H Read Only †These bits program the UPROM cells. Once these bits are programmed, they cannot be erased, and dynamic failure analysis of the device is impossible. 10.
PROGRAMMING THE NONVOLATILE MEMORY VCC 20 pF 20 pF 100 kΩ XTAL1 XTAL2 Reset RESET# VCC +5.0V 1.0µF VCC READY/P5.6 VSS NMI BUSWIDTH/P5.7 EA# 1 kΩ 74HC14 10µF VPP +12.50V VCC VREF RD#/P5.3 P0.7/ PMODE.3 OE# P0.6/ PMODE.2 P0.5/ PMODE.1 CE# A16 A15 A14 P1.3 P1.2 P1.1 A13:8 AD13:8 P0.4/ PMODE.0 VCC ANGND 270kΩ ALE/P5.0 LE OE# 27(C)512 AD7:0 74LS373 ON = Programming VCC A7:0 O7:0 P2.7/PACT# 74HC14 P2.5 P2.4 P2.3 P2.2 P2.1 270kΩ P2.
87C196CB SUPPLEMENT Table 10-4. Serial Port Programming Mode Memory Map Address Range Description Internal OTPROM Normal Operation Serial Port Programming Mode FF2000–FF7FFFH FF8000–FFFFFFH A000–FFFFH (bank 0; 1FF9H = 00H) 8000–FFFFH (bank 1; 1FF9H = 80H) External memory — 4000–7FFFH Do not address — 2400–3FFFH Test ROM and RISM — 2000–23FFH The lower 24 Kbytes of OTPROM (FF2000–FF7FFFH) are remapped to A000–FFFFH, and the upper 32 Kbytes (FF8000–FFFFFFH) are mapped to 8000–FFFFH.
A Signal Descriptions
APPENDIX A SIGNAL DESCRIPTIONS A.1 FUNCTIONAL GROUPINGS OF SIGNALS Table A-1 lists the signals for the 87C196CB, grouped by function. A diagram of each package that is currently available shows the pin location of each signal. NOTE As new packages are supported, they will be added to the datasheets first. If your package type is not shown in this appendix, refer to the latest datasheet to find the pin locations. Table A-1.
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 P5.2 / WR# / WRL# / SLPWR# P5.5 / BHE# / WRH# P5.3 / RD# / SLPRD# V PP P5.0 / ADV# /ALE / SLPALE P5.1 / INST / SLPCS# P5.6 / READY P5.4 / SLPINT A19 / EPORT.3 VCC VSS1 VSS RXCAN TXCAN XTAL1 XTAL2 P6.7 / SD1 P6.6 / SC1 P6.5 / SD0 P6.4 / SC0 VCC 87C196CB Supplement 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 xx87C196CB View of component as mounted on PC board 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 PLLEN P6.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 xx87C196CB View of component as mounted on PC board 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P5.7 / BUSWIDTH P5.2 / WR# / WRL# / SLPWR# P5.5 / BHE# / WRH# P5.3 / RD# / SLPRD# A20 / EPORT.4 A21 / EPORT.5 A22 / EPORT.6 VPP A23 / EPORT.7 P5.0 / ADV# / ALE / SLPALE P5.1 / INST / SLPCS# P5.6 / READY P5.4 / SLPINT A19 / EPORT.3 NC VCC NC VSS1 VSS NC RXCAN TXCAN XTAL1 XTAL2 NC P6.
87C196CB Supplement Table A-2. Description of Columns of Table A-3 Column Heading Description Name Lists the signals, arranged alphabetically. Many pins have two functions, so there are more entries in this column than there are pins. Every signal is listed in this column. Type Identifies the pin function listed in the Name column as an input (I), output (O), bidirectional (I/O), power (PWR), or ground (GND). Note that all inputs except RESET# are sampled inputs. RESET# is a levelsensitive input.
SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions (Continued) Name ADV# Type O Description Address Valid This active-low output signal is asserted only during external memory accesses. ADV# indicates that valid address information is available on the system address/data bus. The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. An external latch can use this signal to demultiplex the address from the address/data bus.
87C196CB Supplement Table A-3. Signal Descriptions (Continued) Name BREQ# Type O Description Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. The device can assert BREQ# at the same time as or after it asserts HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is removed. You must enable the bus-hold protocol before using this signal. BREQ# is multiplexed with P2.3.
SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions (Continued) Name EA# Type I Description External Access This input determines whether memory accesses to special-purpose and program memory partitions (FF2000–FF9FFFH) are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant. EA# also controls entry into programming mode.
87C196CB Supplement Table A-3. Signal Descriptions (Continued) Name HLDA# Type O Description Bus Hold Acknowledge This active-low output indicates that the CPU has released the bus as the result of an external device asserting HOLD#. HLDA# is multiplexed with P2.6 and CPVER. HOLD# I Bus Hold Request An external device uses this active-low input signal to request control of the bus. This pin functions as HOLD# only if the pin is configured for its special function and the bus-hold protocol is enabled.
SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions (Continued) Name P0.7:0 Type I Description Port 0 This is a high-impedance, input-only port. Port 0 pins should not be left floating. These pins may individually be used as analog inputs (ACHx) or digital inputs (P0.x). While it is possible for the pins to function simultaneously as analog and digital inputs, this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results.
87C196CB Supplement Table A-3. Signal Descriptions (Continued) Name P6.7:0 Type I/O Description Port 6 This is a standard 8-bit bidirectional port. Port 6 is multiplexed as follows: P6.0/EPA8/COMP0, P6.1/EPA9/COMP1, P6.2/T1CLK, P6.3/T1DIR, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1. PACT# O Programming Active During auto programming or ROM-dump, a low signal indicates that programming or dumping is in progress, while a high signal indicates that the operation is complete. PACT# is multiplexed with P2.
SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions (Continued) Name PROG# Type I Description Programming Start During programming, a falling edge latches data on the PBUS and begins programming, while a rising edge ends programming. The current location is programmed with the same data as long as PROG# remains asserted, so the data on the PBUS must remain stable while PROG# is active.
87C196CB Supplement Table A-3. Signal Descriptions (Continued) Name Type SD1:0 I/O SLP7:0 I/O Description Data Pins for SSIO0 and 1 SD0 is multiplexed with P6.5, and SD1 is multiplexed with P6.7. Slave Port Address/Data bus Slave port address/data bus in multiplexed mode and slave port data bus in demultiplexed mode. In multiplexed mode, SLP1 is the source of the internal control signal, SLP_ADDR. SLP7:0 are multiplexed with AD7:0, P3.7:0, and PBUS.7:0.
SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions (Continued) Name T2DIR Type I Description Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. Also used in conjunction with T2CLK for quadrature counting mode. T2DIR is multiplexed with P1.2 and EPA2. TXCAN O Transmit This signal carries messages from the integrated CAN controller to other nodes on the CAN bus.
87C196CB Supplement Table A-3. Signal Descriptions (Continued) Name Type WRL# Description O Write Low† During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# is multiplexed with P5.2, SLPWR#, and WR#. † The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
SIGNAL DESCRIPTIONS Table A-5. 87C196CB Pin Status (Continued) Port Pins Multiplexed With Status During Reset Status During Idle Status During Powerdown P2.2 EXTINT WK1 (Note 3) (Note 3) P2.3 BREQ# WK1 (Note 3) (Note 3) P2.4 INTOUT# WK1 (Note 3) (Note 3) P2.5 HOLD# WK1 (Note 3) (Note 3) P2.6 HLDA# WK1 (Note 3) (Note 3) P2.7 CLKOUT CLKOUT active, LoZ0/1 (Note 3) (Note 4) P3.7:0 AD7:0 WK1 (Note 6) (Note 6) P4.7:0 AD15:8 WK1 (Note 6) (Note 6) EPORT.
Glossary
GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this manual. (Chapter 1 discusses notational conventions and general terminology.) absolute error The maximum difference between corresponding actual and ideal code transitions. Absolute error accounts for all deviations of an actual A/D converter from an ideal converter. accumulator A register or storage location that forms the result of an arithmetic or logical operation.
87C196CB SUPPLEMENT CAN Controller area network. The 87C196CB’s integrated networking peripheral, similar to Intel’s standalone 82527 CAN serial communications controller, that supports CAN specification 2.0. CCBs Chip configuration bytes. The chip configuration registers (CCRs) are loaded with the contents of the CCBs after a device reset, unless the device is entering programming modes, in which case the PCCBs are used. CCRs Chip configuration registers.
GLOSSARY code width The voltage change corresponding to the difference between two adjacent code transitions. Code width deviations cause differential nonlinearity and nonlinearity errors. crosstalk See off-isolation. DC input leakage Leakage current from an analog input pin to ground. deassert The act of making a signal inactive (disabled). The polarity (high or low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix.
87C196CB SUPPLEMENT FET Field-effect transistor. frequency generator The 8XC196MD peripheral that generates outputs with a fixed 50% duty cycle and a programmable frequency. The frequency generator can be used for infrared transmission. full-scale error The difference between the ideal and actual input voltage corresponding to the final (full-scale) code transition of an A/D converter. hold latency The time it takes the microcontroller to assert HLDA# after an external device asserts HOLD#.
GLOSSARY ISR See interrupt service routine. linearity errors See differential nonlinearity and nonlinearity. LONG-INTEGER A 32-bit, signed variable with values from –231 through +231–1. LSB 1) Least-significant bit of a byte or least-significant byte of a word. 2) In an A/D converter, the reference voltage divided by 2n, where n is the number of bits to be converted. For a 10-bit converter with a reference voltage of 5.12 volts, one LSB is equal to 5.0 millivolts (5.12 ÷ 210).
87C196CB SUPPLEMENT nonlinearity The maximum deviation of code transitions of the terminal-based characteristic from the corresponding code transitions of the ideal characteristic. nonmaskable interrupts Interrupts that cannot be masked (disabled) and cannot be assigned to the PTS for processing. The nonmaskable interrupts are unimplemented opcode, software trap, and NMI. nonvolatile memory Read-only memory that retains its contents when power is removed.
GLOSSARY prioritized interrupt Any maskable interrupt or nonmaskable NMI. Two of the nonmaskable interrupts (unimplemented opcode and software trap) are not prioritized; they vector directly to the interrupt service routine when executed. program memory A partition of memory where instructions can be stored for fetching and execution. protected instruction An instruction that prevents an interrupt from being acknowledged until after the next instruction executes.
87C196CB SUPPLEMENT PTS transfer The movement of a single byte or word from the source memory location to the destination memory location. PTS vector A location in special-purpose memory that holds the starting address of a PTS control block. PWM Pulse-width modulated (outputs). The 8XC196Mx devices have several options for producing PWM outputs: the generic pulse-width modulator modules, the waveform generator, and the EPA with or without the PTS.
GLOSSARY sample delay The time period between the time that A/D converter receives the “start conversion” signal and the time that the sample capacitor is connected to the selected channel. sample delay uncertainty The variation in the sample delay. sample time The period of time that the sample window is open. (That is, the length of time that the input channel is actually connected to the sample capacitor.) sample time uncertainty The variation in the sample time.
87C196CB SUPPLEMENT source current Current flowing out of a device from VCC. Always a negative value. SP Stack pointer. special interrupt Any of the three nonmaskable interrupts (unimplemented opcode, software trap, or NMI). special-purpose memory A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and several reserved locations.
GLOSSARY transfer function errors Errors inherent in an analog-to-digital conversion process: quantizing error, zero-offset error, full-scale error, differential nonlinearity, and nonlinearity. Errors that are hardware-dependent, rather than being inherent in the process itself, include feedthrough, repeatability, channel-to-channel matching, offisolation, and VCC rejection errors. UART Universal asynchronous receiver and transmitter. A part of the serial I/O port.
Index
INDEX A A/D converter, signals, 6-1 AD_COMMAND register, 6-2 AD_RESULT register, 6-3 Auto programming mode circuit, 10-3 memory map, 10-2 B Block diagram CAN peripheral, 7-2 clock circuitry, 2-2 core and peripherals, 2-2 Bus-timing modes, 9-1–9-2 comparison, 9-1, 9-2 C CAN serial communications controller, 7-1–7-42 address map, 7-5 bit timing, 7-10–7-12 block diagram, 7-2 bus-off state, 7-41 error detection and management logic, 7-9 message acceptance filtering, 7-6 frames, 7-7 extended, 7-8 standard, 7-8
87C196CB SUPPLEMENT P P0_PIN register, 5-1 Period (t), 2-4 Pin diagrams, A-1 Pins, reset status, A-14–A-15 Port 0, 5-1 Powerdown mode, pin status, A-14 R Registers AD_COMMAND, 6-2 AD_RESULT, 6-3 CAN_BTIME0, 7-3, 7-15 CAN_BTIME1, 7-3, 7-16 CAN_CON, 7-3, 7-13, 7-29 CAN_EGMSK, 7-3, 7-19 CAN_INT, 7-3, 7-32 CAN_MSGxCFG, 7-3, 7-21 CAN_MSGxCON0, 7-3, 7-24, 7-31, 7-34 CAN_MSGxCON1, 7-4, 7-26 CAN_MSGxDATA0-7, 7-28 CAN_MSGxDATAx, 7-4 CAN_MSGxID, 7-4 CAN_MSGxID0-3, 7-22 CAN_MSK15, 7-4, 7-20 CAN_SGMSK, 7-4, 7-18 CAN_
