21555 PCI-to-PCI Bridge Evaluation Board User’s Guide November 2002 Order Number: 278359-002
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Contents 1 Introduction......................................................................................................................... 5 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 Operations and Installation...............................................................................................17 2.1 2.2 2.3 2.4 2.5 3 Overview ............................................................................................................... 5 Features ..........................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 iv DIP Switch Operation............................................................................................ 9 Stake-Pin Jumper ................................................................................................. 9 Clock Configuration Jumpers .............................................................................. 11 Voltage Clamp.....................................................................................................
Introduction 1 This User’s Guide describes the 21555 PCI-to-PCI nontransparent Bridge Evaluation Board which is referred to as the DE1B55503. 1.1 Overview The DE1B55503 is a PCI expansion board that is used to evaluate the operation of the 21555 when it is used as a gateway to an intelligent subsystem. The subsystem can use a variety of PCI devices and local processors.
Introduction 1.3 Major Components Figure 1 on page 6 shows the major components on the DE1B55503. Figure 1.
Introduction Note: 1.3.2 See Table A-2 on page 24 for Mictor pinouts. Switches and Jumper The DE1B55503 uses a combination of DIP switch, stake-pin and zero ohm resistor jumpers to control the various configuration options. See Section 1.4, Section 1.5, and Section 1.6 for information. • J8 is a single stake pin jumper. See Section 1.5 for information. • J9, J20, and J21 are five-switch switch packs. The dual-pole switches are labeled SW1 through SW5.
Introduction 1.4 Switch Settings Figure 2 shows the three initialization switch packs, and Table 1 on page 9 gives a high-level description of each switch. The switches are read at DE1B55503 power up. Further details on the operation of these switches can be found in Chapter 3, “Optional Configurations”. The switches are in dual-in-line (DIP) packs designated J9, J20, and J21. Each switch pack contains SW1 through SW5. Figure 2.
Introduction Table 1. DIP Switch Operation Switch Pack Switch The Switch Controls Reference Information SW1, 2, 3 PICMG configurations. (See Chapter 3). Table 10 on page 21 SW4 PR_AD1 strapping option. 21555 Non Transparent PCI-to-PCI Bridge User’s Manual SW5 PR_CS to either Flash or optional ROM socket. Table 8 on page 19 SW1 PR_AD2 for SROM operation. SW2 PR-AD3 for lockout bit control. SW3 PR_AD4 for synchronous or asynchronous clocking. SW4 PR_AD5 for S_CLKO operation.
Introduction 1.6 Resistor Jumpers Figure 3 shows the location of the zero (0) ohm resistor configuration jumpers. They control the clock configuration and the clamping voltage. To alter the factory configuration of the DE1B55503, the jumpers must be soldered on or off the DE1B55503 board. See Appendix A, “Signal and Default Information”. Figure 3.
Introduction 1.6.1 Clock Configuration Table 3 describes the resistor jumpers to install that connect p_clk and s_clk_o to the Mictor connectors. To improve signal integrity and minimize noise, these signals are not wired to the Mictor connectors. Resistor jumpers also control the selection of clock signals. See Figure 3 on page 10 for the resistor jumper locations. See Table A-3 on page 24 for Mictor pinouts. Table 3. 1.6.
Introduction 1.7 Secondary Slot Numbering and IDSEL Mapping Figure 4 gives the bus slot numbering. Table 5 shows how a Product Name numbers the Local slots in response to a Type 0 or Type 1 configuration cycle. The local bus lines s_ad<24> and s_ad<31:28> are used as local Initilization Device Select (IDSEL) lines. Figure 4.
Introduction 1.8 Interrupt Routing Table 6 shows the ORing of interrupts. 12 interrupts are connected to each of three secondary bus PCI slots but four (4) interrupts are driven to the card edge. The 12 incoming interrupts must be combined. Interrupt ORing is in accordance with the PCI-to-PCI Bridge Architecture Specification revision 1.1. Table 6.
Introduction 1.9 Typical Configurations Figure 5 shows the DE1B55503 with one local bus option card. The option card can be either 32-bit or 64-bit. Figure 5.
Introduction Figure 6 shows the DE1B55503 with two local bus option cards. Figure 6.
Operations and Installation 2 This chapter provides DE1B55503 specifications and information about the hardware and software requirements for using the DE1B55503. It also describes how to install the DE1B55503. 2.1 Specifications This sections describes some overall specifications for the DE1B55503 board: Physical dimensions: • Height: 15.2 cm (6.0 in) • Width: 17.8 cm (7.0 in) Power requirements: • DC amps @ 5 V: 2 A (maximum) • On Board 3.3V regulator for S_VIO and Vdd 5A (Maximum) 2.
Operations and Installation • MSKROM.EXE an executable utility for programming the SROM. • The software diskettes are standard 3.5 inch floppy disks. Follow the installation procedure printed on the inside of the shipping package. Be certain that the target system meets the minimum system requirements. 2.3.1 Programming the SROM To program the SROM on the DE1B55503, use the MKSROM.EXE utility. Use a text editor to create an ASCII data file. MSKSROM file.dat Where: MSKROM Executes the MSKROM utility.
Operations and Installation 2.3.2.1 Board Setup Table 8 gives the DE1B55503 switch configuration for using the DBFLASH.EXE utility. Table 8. Switch Operation for FLASH programming Switch Pack Switch Switch Down Switch Upa Description J9 SW5 ROM Socket pr_cs Program and access memory using DBFLASH.EXE. Enables DBFLASH access to the ROM Socket or to the flash memory. See Figure 1 on page 6. a. Default configuration. 2.3.2.2 Running DbFlash.exe Make sure that both DBFLASH.EXE and DOS4GW.
Operations and Installation connectors and one (1) connector-less slot. Section 1.9, “Typical Configurations” on page 14 shows examples of typical PCI configurations. 6. Apply power to the system. 7. Verify the auto-configuration of the 21555 and other options. a. If the on-board ROM is preloaded the 21555 banner displays. b. Verify that system BIOS or firmware detects and configures the 21555. c. To verify the loading of the SROM, run the MKSROM utility without an SROM file as an input. See Section 2.3.
3 Optional Configurations 3.1 PICMG Configuration This section describes how to configure the DE1B55503 to have a Single Board Computer (SBC) with a PCI interface as defined in the PICMG PCI-ISA Interface Specification. See Section 1.3.1, “Connectors” on page 6. The DE1B55503 can have an intelligent subsystem installed that supports the local bus. The intelligent subsystem is architecture independent. The 21555 can interface to any intelligent subsystem that has a PCI interface.
Optional Configurations • In the other configuration, the central function is controlled by the intelligent subsystem through the J1 connector. Table 12. External Arbiter Switch Option Switch Pack Switch J20 J21 Switch Down Switch Up SW5 Enable the 21555 as central arbiter System slot (J102) as Central Function SW1 Disable the 21555 System slot (J102) as as central arbiter external arbiter. Description Central Function Mode(pr_ad<6>) Disable 21555 arbiter.
Signal and Default Information A.1 A J2 J4, J5, and J6 Connector Pinouts Table A-1 gives the Mictor connectors pin assignment and DE1B55503 schematic signal names. See Figure 1 on page 6 for the location of this connector. Table A-1.
Signal and Default Information Table A-2 gives the Mictor connectors pin assignment and DE1B55503 schematic signal names. Table A-2.
Signal and Default Information Table A-3. J5 CBE, REQ, and GNT Schematic Signal Name Mictor Pin Number Mictor Pin Number Schematic Signal Name S_REQ8 23 24 S_GNT1 S_REQ7 25 26 S_GNT0 S_REQ6 27 28 S_M66ENA S_REQ5 29 30 S_PNE S_REQ4 31 32 S_REQ3 33 34 S_CLKI S_REQ2 35 36 SCLK_O S_REQ1 37 38 Table A-4 gives the Mictor connectors pin assignment and DE1B55503 schematic signal names. Table A-4.
Signal and Default Information A.2 JATAG Connector Pinout Table A-5 gives the pin assignments between the DE1B55503 schematic and the ten-pin JTAG connector. See Figure 1 on page 6 for the location of this connector. Table A-5. J1 JATAG Connector A.
