User Manual

34 Intel® Xeon® Processor E5-2600 v4 Product Family
Specification Update December 2016
MEM_HOT_C23_N signal as an input to throttle DIMM activity as needed. See Grantley
Platform Design Guide Rev. 2.2, IBL ID: 506549 for further details.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF83 Bi-Directional PCIe* Posted Transactions May Lead to System Hang
Problem: Certain bi-directional PCIe posted traffic patterns between CPU nodes may lead to a
loss of flow control credits resulting in a link hang.
Implication: Deadlock on a PCIe link may result in a system hang.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes
BDF84 Excessive Uncorrected and Corrected Memory Errors May Occur
Following S3 Resume or Warm Reset
Problem: Following S3 resume or warm reset, uncorrected and corrected memory errors may
occur.
Implication: When this erratum occurs, the system will log correctable errors, signal a machine
check, or shut down.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF85 Writing MSR_LASTBRANCH_x_FROM_IP May #GP When Intel® TSX is
Not Supported
Problem: Due to this erratum, on processors that do not support Intel TSX (Intel® Transactional
Synchronization Extensions) (CPUID.07H.EBX bits 4 and 11 are both zero), writes to
MSR_LASTBRANCH_x_FROM_IP (MSR 680H to 68FH) may #GP unless bits[62:61] are
equal to bit[47].
Implication: The value read from MSR_LASTBRANCH_x_FROM_IP is unaffected by this erratum; bits
[62:61] contain IN_TSX and TSX_ABORT information respectively. Software restoring
these MSRs from saved values are subject to this erratum.
Workaround: Before writing MSR_LASTBRANCH_x_FROM_IP, ensure the value being written has
bit[47] replicated in bits[62:61]. This is most easily accomplished by sign extending
from bit[47] to bits[62:48].
Status: For the Steppings affected, see the Summary Tables of Changes.
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