User Manual

Intel® Xeon® Processor E5-2600 v4 Product Family 31
Specification Update December 2016
BDF68 PEBS Record May Be Generated After Being Disabled
Problem: A performance monitoring counter may generate a PEBS (Precise Event Based
Sampling) record after disabling PEBS or the performance monitoring counter by
clearing the corresponding enable bit in IA32_PEBS_ENABLE MSR (3F1H) or
IA32_PERF_GLOBAL_CTRL MSR (38FH).
Implication: A PEBS record generated after a VMX transition will store into memory according to the
post-transition DS (Debug Store) configuration. These stores may be unexpected if
PEBS is not enabled following the transition.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. A software
workaround is possible through disallowing PEBS during VMX non-root operation and
disabling PEBS prior to VM entry.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF69 Software Using Intel® TSX May Behave Unpredictably
Problem: Under a complex set of internal timing conditions and system events, software using
the Intel TSX (Transactional Synchronization Extensions) instructions may behave
unpredictably.
Implication: This erratum may result in unpredictable behavior of the software using TSX.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF70 Some E5-1607V4 And E5-1603V4 Parts Will Incorrectly Report
Support For DDR4-2400
Problem: Some E5-1607V4 and E5-1603V4 parts will incorrectly report that they support DDR4-
2400. Using DDR4-2400 DIMMs may result in unpredictable system behavior.
Implication: System may operate their memory sub-systems at DDR4-2400 rather than DDR4-
2133.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF71 PROCHOT# Assertion During Warm Reset May Cause Persistent
Performance Reduction
Problem: Assertion of PROCHOT# after RESET# de-assertion but before BIOS has completed
reset initialization (indicated by CPL3) may result in persistent processor throttling.
Asserting PROCHOT# during and after RESET# assertion for FRB (Fault Resilient Boot)
tri-stating of the processor is not affected by this erratum.
Implication: When this erratum occurs, the resultant persistent throttling substantially reduces the
processor’s performance.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF72 Data Breakpoint Coincident With a Machine Check Exception May be
Lost
Problem: If a data breakpoint occurs coincident with a machine check exception, then the data
breakpoint may be lost.
Implication: Due to this erratum, a valid data breakpoint may be lost.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.