User Manual

30 Intel® Xeon® Processor E5-2600 v4 Product Family
Specification Update December 2016
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF63 A #VE May Not Invalidate Cached Translation Information
Problem: An EPT (Extended Page Table) violation that causes a #VE (virtualization exception)
may not invalidate the guest-physical mappings that were used to translate the guest-
physical address that caused the EPT violation.
Implication: Due to this erratum, the system may hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF64 Package C-state Transitions While Inband PECI Accesses Are in
Progress May Cause Performance Degradation
Problem: When a Package C-state transition occurs at the same time an inband PECI transaction
occurs, PROCHOT# may be incorrectly asserted.
Implication: Incorrect assertion of PROCHOT# reduces the core frequency to the minimum
operating frequency of 1.2 GHz resulting in persistent performance degradation.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
BDF65 Attempting Concurrent Enabling of Intel® Processor Trace (Intel® PT)
With LBR, BTS, or BTM Results in a #GP
Problem: If LBR (Last Branch Records), BTS (Branch Trace Store), or BTM (Branch Trace
Messages) are enabled in the IA32_DEBUGCTL MSR (1D9H), an attempt to enable Intel
PT (Intel® Processor Trace) in IA32_RTIT_CTL MSR (570H) results in a #GP (general
protection exception). (Note that the BTM enable bit in IA32_DEBUGCTL MSR is named
“TR”.) Correspondingly, if Intel PT was previously enabled when an attempt is made to
enable LBR, BTS, or BTM, a #GP will occur.
Implication: An unexpected #GP may occur when concurrently enabling any one of LBR, BTS, or
BTM with Intel PT.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF66 A DDR4 C/A Parity Error in Lockstep Mode May Result in a Spurious
Uncorrectable Error
Problem: If a memory C/A (Command/Address) parity error occurs while the memory subsystem
is configured in lockstep mode then the channel that observed the error will properly
log the error but the associated channel in lockstep will incorrectly log an uncorrectable
error in its IA32_MCi_STATUS MSR.
Implication: Due to this erratum, incorrect logging of an uncorrectable memory error in
IA32_MCi_STATUS may occur.
Status: A BIOS code change has been identified and may be implemented as a workaround for
this erratum
BDF67 Cores May be Unable to Reach Maximum Turbo Frequency
Problem: Due to this erratum, processors with more than ten cores may be limited to less than
the specified maximum turbo frequency.
Implication: When this erratum occurs, the processor performance is reduced.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.