User Manual

Intel® Xeon® Processor E5-2600 v4 Product Family 29
Specification Update December 2016
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF57 Writing MSR_ERROR_CONTROL May Cause a #GP
Problem: A WRMSR that attempts to set MODE1_MEMERROR_REPORT field (bit 1) and/or
MEM_CORRERR_LOGGING_DISABLE field (bit 5) of the MSR_ERROR_CONTROL MSR
(17FH) may incorrectly cause a #GP (General Protection exception).
Implication: Due to this erratum, if BIOS attempts to change the value of the listed bits, a #GP may
occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF58 Enabling ACC in VMX Non-Root Operation May Cause System
Instability
Problem: ACC (Autonomous C-State Control) is enabled by setting ACC_Enable (bit 16) of
MSR_PKG_CST_CONFIG_CONTROL (E2H) to ‘1’. If ACC is enabled while the processor
is in VMX non-root operation, an unexpected VM exit, a machine check, or
unpredictable system behavior may result.
Implication: Enabling ACC may lead to system instability.
Workaround: None identified. BIOS should not enable ACC.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF59 A Spurious Patrol Scrub Error May be Logged
Problem: When a memory ECC error occurs, a spurious patrol scrub error may also be logged on
another memory channel.
Implication: A patrol scrub correctable error may be incorrectly logged.
Workaround: The Home Agent error registers and correctable error count registers (Bus 1; Device
20; Function 2; Offset 104-110) provides accurate error information.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF60 Performance Monitoring Counters May Produce Incorrect Results for
BR_INST_RETIRED Event on Logical Processor.
Problem: Performance monitoring event BR_INST_RETIRED (C4H) counts retired branch
instructions. Due to this erratum, when operating on logical processor 1 of any core,
BR_INST_RETIRED.FAR_BRANCH (Event C4H; Umask 40H) and BR_INST_RETIRED.
ALL_BRANCHES (Event C4H; Umask 04H) may count incorrectly. Logical processor 0 of
all cores and cores with SMT disabled are not affected by this erratum.
Implication: Due to this erratum, certain performance monitoring event may produce unreliable
results when SMT is enabled.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF61 Removed.
BDF62 Processor Instability May Occur When Using The PECI RdIAMSR
Command
Problem: Under certain circumstances, reading a machine check register using the PECI
(Platform Environmental Control Interface) RdIAMSR command may result in a
machine check, processor hang or shutdown.
Implication: Machine check, hang or shutdown may be observed when using the PECI RdIAMSR
command.