User Manual

28 Intel® Xeon® Processor E5-2600 v4 Product Family
Specification Update December 2016
BDF52 Processor Does Not Check IRTE Reserved Bits
Problem: As per the Intel® Virtualization Technology for Directed I/O (Intel® VT-d) specification,
bits 63:HAW (Host Address Width) of the Posted Interrupt Descriptor Upper Address
field in the IRTE (Interrupt Remapping Table Entry) must be checked for a value of 0;
violations must be reported as an interrupt-remapping fault. Due to this erratum,
hardware does not perform this check and does not signal an interrupt-remapping fault
on violations.
Implication: If software improperly programs the reserved address bits of posted interrupt
descriptor upper address in the IRTE to a value other than zero, hardware will not
detect and report the violation.
Workaround: Software must ensure posted interrupt address bits 63:HAW in the IRTE are zero.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF53 PCIe* TPH Request Capability Structure Incorrectly Advertises Device
Specific Mode as Supported
Problem: The TPH (Transaction layer packet Processing Hints) Requester Capability Structure
(PCI Express Extended Capability ID type 0017H) incorrectly reports that Device
Specific Mode is supported in its TPH Requester Capability Register (bit 2 at offset 04H
in the capability structure).
Implication: The processor supports only No ST (Steering Tag) Mode. The PCI Express Base
Specification allows, in this instance, the TPH Requester Capability Structure’s TPH
Requester Control Register (at offset 08H) bits 2:0 to be hardwired to ‘000’,
forcing No ST Mode. Advertising Device Specific Mode but forcing No ST Mode is a
violation of the PCI Express Base Specification (and may be reported as a compliance
issue). Intel has not observed this erratum to impact the operation of any commercially
available system.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF54 Package C3 State or Deeper May Lead to a Reset
Problem: Due to this erratum, the processor may reset and signal a Machine Check error with a
IA32_MCi_STATUS.MCACOD value of 0400H when in Package C3 state or deeper.
Implication: When this erratum occurs, the processor will reset and report an uncorrectable
machine check error.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum. It is possible for the BIOS to contain a workaround for this erratum
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF55 VMX-Preemption Timer May Stop Operating When ACC is Enabled
Problem: When the MSR_PKG_CST_CONFIG_CONTROL.ACC_Enable bit (MSR E2H, bit 16) is set,
the VMX-preemption timer is not decremented in the HLT state.
Implication: When ACC (Autonomous C-State Control) is enabled, the VMX-preemption timer may
not cause a VM exit when expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF56 Intel® Advanced Vector Extensions (Intel® AVX) Workloads May
Exceed ICCMAX Limits
Problem: Intel AVX workloads require a reduced maximum turbo ratio. Due to this erratum, the
Intel AVX turbo ratio is higher than expected which may cause the processor to exceed
ICCMAX limits and lead to unpredictable system behavior.
Implication: Due to this erratum, the processor may exhibit unpredictable system behavior.