User Manual

Intel® Xeon® Processor E5-2600 v4 Product Family 27
Specification Update December 2016
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF47 General-Purpose Performance Counters May be Inaccurate with Any
Thread
Problem: The IA32_PMCx MSR (C1H - C8H) general-purpose performance counters may report
inaccurate counts when the associated event selection IA32_PERFEVTSELx MSR’s
(186H - 18DH) AnyThread field (bit 21) is set and either.
Implication: Due to this erratum, IA32_PMCx counters may be inaccurate.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF48 An Invalid LBR May Be Recorded Following a Transactional Abort
Problem: Use of Intel
®
Transactional Synchronization Extensions may result in a transactional
abort. If an abort occurs immediately following a branch instruction, an invalid LBR
(Last Branch Record) may be recorded before the LBR produced by the abort.
Implication: The invalid LBR may interfere with execution path reconstruction prior to the
transactional abort.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF49 Executing an RSM Instruction With Intel® Processor Trace Enabled
Will Signal a #GP
Problem: Upon delivery of an SMI (System Management Interrupt), the processor saves and
then clears TraceEn in the IA32_RTIT_CTL MSR (570H), thus disabling Intel® Processor
Trace (Intel® PT). If the SMI handler enables Intel PT and it remains enabled when an
RSM instruction is executed, a shutdown event should occur. Due to this erratum, the
processor does not shutdown but instead generates a #GP (general-protection
exception).
Implication: When this erratum occurs, a #GP will be signaled.
Workaround: If software enables Intel PT in system-management mode, it should disable Intel® PT
before executing RSM.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF50 Intel® Processor Trace PIP May be Unexpectedly Generated
Problem: When Intel® Processor Trace is enabled, PSB+ (Packet Stream Boundary) packets may
include a PIP (Paging Information Packet) even though the OS field (bit 2) of
IA32_RTIT_CTL MSR (570H) is 0.
Implication: When this erratum occurs, user-mode tracing (indicated by IA32_RTIT_CTL.OS = 0)
may include CR3 address information. This may be an undesirable leakage of kernel
information.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF51 Processor Core Ratio Changes While in Probe Mode May Result in a
Hang
Problem: If a processor core ratio change occurs while the processor is in probe mode, the
system may hang.
Implication: Due to this erratum, the processor may hang.
Workaround: None identified. Processor core ratio changes may be disabled to avoid this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.