User Manual

26 Intel® Xeon® Processor E5-2600 v4 Product Family
Specification Update December 2016
memory destination of that instruction may return the value that was in memory before
the transactional region began.
Implication: Due to this erratum, unpredictable system behavior may occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF42 Removed.
BDF43 Performance Monitoring Event INSTR_RETIRED.ALL May Generate
Redundant PEBS Records For an Overflow
Problem: Due to this erratum, the performance monitoring feature PDIR (Precise Distribution of
Instructions Retired) for INSTR_RETIRED.ALL (Event C0H; Umask 01H) will generate
redundant PEBS (Precise Event Based Sample) records for a counter overflow. This can
occur if the lower 6 bits of the performance monitoring counter are not initialized or
reset to 0, in the PEBS counter reset field of the DS Buffer Management Area.
Implication: The performance monitor feature PDIR, may generate redundant PEBS records for an
overflow.
Workaround: Initialize or reset the counters such that lower 6 bits are 0.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF44 Reset During PECI Transaction May Cause a Machine Check Exception
Problem: If a PECI transaction is interrupted by a warm reset, it may result in a machine check
exception with MCACOD of 0x402.
Implication: When this erratum occurs, the system becomes unresponsive and a machine check will
be generated.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF45 Intel® Processor Trace (Intel® PT) MODE.Exec, PIP, and CBR Packets
Are Not Generated as Expected
Problem: The Intel® PT MODE.Exec (MODE packet – Execution mode leaf), PIP (Paging
Information Packet), and CBR (Core: Bus Ratio) packets are generated at the following
PSB+ (Packet Stream Boundary) event rather than at the time of the originating event
as expected.
Implication: The decoder may not be able to properly disassemble portions of the binary or interpret
portions of the trace because many packets may be generated between the
MODE.Exec, PIP, and CBR events and the following PSB+ event.
Workaround: The processor inserts these packets as status packets in the PSB+ block. The decoder
may have to skip forward to the next PSB+ block in the trace to obtain the proper
updated information to continue decoding.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF46 Performance Monitor Instructions Retired Event May Not Count
Consistently
Problem: The Performance Monitor Instructions Retired event (Event C0H; Umask 00H) and the
instruction retired fixed counter IA32_FIXED_CTR0 MSR (309H) are used to count the
number of instructions retired. Due to this erratum, certain internal conditions may
cause the counter(s) to increment when no instruction has retired or to intermittently
not increment when instructions have retired.
Implication: A performance counter counting instructions retired may over count or under count.
The count may not be consistent between multiple executions of the same code.
Workaround: None identified.