User Manual

Intel® Xeon® Processor E5-2600 v4 Product Family 25
Specification Update December 2016
BDF37 VM Exit May Set IA32_EFER.NXE When IA32_MISC_ENABLE Bit 34 is
Set to 1
Problem: When “XD Bit Disable” in the IA32_MISC_ENABLE MSR (1A0H) bit 34 is set to 1, it
should not be possible to enable the “execute disable” feature by setting
IA32_EFER.NXE. Due to this erratum, a VM exit that occurs with the 1-setting of the
“load IA32_EFER” VM-exit control may set IA32_EFER.NXE even if IA32_MISC_ENABLE
bit 34 is set to 1. This erratum can occur only if IA32_MISC_ENABLE bit 34 was set by
guest software in VMX non-root operation.
Implication: Software in VMX root operation may execute with the “execute disable” feature enabled
despite the fact that the feature should be disabled by the IA32_MISC_ENABLE
MSR. Intel has not observed this erratum with any commercially available software.
Workaround: A virtual-machine monitor should not allow guest software to write to the
IA32_MISC_ENABLE MSR.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF38 A MOV to CR3 When EPT is Enabled May Lead to an Unexpected Page
Fault or an Incorrect Page Translation
Problem: If EPT (extended page tables) is enabled, a MOV to CR3 or VMFUNC may be followed by
an unexpected page fault or the use of an incorrect page translation.
Implication: Guest software may crash or experience unpredictable behavior as a result of this
erratum.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF39 Intel® Processor Trace Packet Generation May Stop Sooner Than
Expected
Problem: Setting the STOP bit (bit 4) in a Table of Physical Addresses entry directs the processor
to stop Intel PT (Processor Trace) packet generation when the associated output region
is filled. The processor indicates this has occurred by setting the Stopped bit (bit 5) of
IA32_RTIT_STATUS MSR (571H). Due to this erratum, packet generation may stop
earlier than expected.
Implication: When this erratum occurs, the OutputOffset field (bits [62:32]) of the
IA32_RTIT_OUTPUT_MASK_PTRS MSR (561H) holds a value that is less than the size of
the output region which triggered the STOP condition; Intel PT analysis software should
not attempt to decode packet data bytes beyond the OutputOffset.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF40 PEBS Eventing IP Field May be Incorrect After Not-Taken Branch
Problem: When a PEBS (Precise-Event-Based-Sampling) record is logged immediately after a
not-taken conditional branch (Jcc instruction), the Eventing IP field should contain the
address of the first byte of the Jcc instruction. Due to this erratum, it may instead
contain the address of the instruction preceding the Jcc instruction.
Implication: Performance monitoring software using PEBS may incorrectly attribute PEBS events
that occur on a Jcc to the preceding instruction.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF41 Reading The Memory Destination of an Instruction That Begins an
HLE Transaction May Return The Original Value
Problem: An HLE (Hardware Lock Elision) transactional region begins with an instruction with the
XACQUIRE prefix. Due to this erratum, reads from within the transactional region of the