User Manual

24 Intel® Xeon® Processor E5-2600 v4 Product Family
Specification Update December 2016
BDF32 Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be
Observed
Problem: During RTM (Restricted Transactional Memory) operation when branch tracing is
enabled using BTM (Branch Trace Message) or BTS (Branch Trace Store), the incorrect
EIP value (From_IP pointer) may be observed for an RTM abort.
Implication: Due to this erratum, the From_IP pointer may be the same as that of the immediately
preceding taken branch.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF33 Locked Load Performance Monitoring Events May Under Count
Problem: The performance monitoring events MEM_TRANS_RETIRED.LOAD_LATENCY (Event
CDH; Umask 01H), MEM_LOAD_RETIRED.L2_HIT (Event D1H; Umask 02H), and
MEM_UOPS_RETIRED.LOCKED (Event DOH; Umask 20H) should count the number of
locked loads. Due to this erratum, these events may under count for locked
transactions that hit the L2 cache.
Implication: The above event count will under count on locked loads hitting the L2 cache.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF34 Transactional Abort May Cause an Incorrect Branch Record
Problem: If an Intel® Transactional Synchronization Extensions (Intel® TSX) transactional abort
event occurs during a string instruction, the From-IP in the LBR (Last Branch Record) is
not correctly reported.
Implication: Due to this erratum, an incorrect FROM-IP on the top of LBR stack may be observed.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF35 PMI May be Signaled More Than Once For Performance Monitor
Counter Overflow
Problem: Due to this erratum, PMI (Performance Monitoring Interrupt) may be repeatedly issued
until the counter overflow bit is cleared in the overflowing counter.
Implication: Multiple PMIs may be received when a performance monitor counter overflows.
Workaround: None identified. If the PMI is programmed to generate an NMI, software may delay the
EOI (end-of- Interrupt) register write for the interrupt until after the overflow
indications have been cleared.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF36 Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a
#NM Exception
Problem: Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a #UD (Invalid-
Opcode) exception. If either the TS or EM flag bits in CR0 are set, a #NM (device-not-
available) exception will be raised instead of #UD exception.
Implication: Due to this erratum a #NM exception may be signaled instead of a #UD exception on
an FXSAVE or an FXRSTOR with a VEX prefix.
Workaround: Software should not use FXSAVE or FXRSTOR with the VEX prefix.
Status: For the Steppings affected, see the Summary Tables of Changes.