User Manual

Intel® Xeon® Processor E5-2600 v4 Product Family 23
Specification Update December 2016
other processor thread does not have on demand clock modulation enabled and that
thread is executing a stream of instructions with the lock prefix that either split a
cacheline or access UC memory.
Implication: Program execution may stall on both threads of the core subject to this erratum.
Workaround: This erratum will not occur if clock modulation is enabled on all threads when using on
demand clock modulation or if the duty cycle programmed in the
IA32_CLOCK_MODULATION MSR is 18.75% or higher.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF28 Performance Monitor Events OTHER_ASSISTS.AVX_TO_SSE And
OTHER_ASSISTS.SSE_TO_AVX May Over Count
Problem: The Performance Monitor events OTHER_ASSISTS.AVX_TO_SSE (Event C1H; Umask
08H) and OTHER_ASSISTS.SSE_TO_AVX (Event C1H; Umask 10H) incorrectly
increment and over count when an HLE (Hardware Lock Elision) abort occurs.
Implication: The Performance Monitor Events OTHER_ASSISTS.AVX_TO_SSE And
OTHER_ASSISTS.SSE_TO_AVX may over count.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF29 Performance Monitor Event DSB2MITE_SWITCHES.COUNT May Over
Count
Problem: The Performance Monitor Event DSB2MITE_SWITCHES.COUNT (Event ABH; Umask
01H) should count the number of DSB (Decode Stream Buffer) to MITE (Macro
Instruction Translation Engine) switches. Due to this erratum, the
DSB2MITE_SWITCHES.COUNT event will count speculative switches and cause the
count to be higher than expected.
Implication: The Performance Monitor Event DSB2MITE_SWITCHES.COUNT may report count higher
than expected.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF30 Timed MWAIT May Use Deadline of a Previous Execution
Problem: A timed MWAIT instruction specifies a TSC deadline for execution resumption. If a wake
event causes execution to resume before the deadline is reached, a subsequent timed
MWAIT instruction may incorrectly use the deadline of the previous timed MWAIT when
that previous deadline is earlier than the new one.
Implication: A timed MWAIT may end earlier than expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF31 IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report The
Highest Index Value Used For VMCS Encoding
Problem: IA32_VMX_VMCS_ENUM MSR (48AH) bits 9:1 report the highest index value used for
any VMCS encoding. Due to this erratum, the value 21 is returned in bits 9:1 although
there is a VMCS field whose encoding uses the index value 23.
Implication: Software that uses the value reported in IA32_VMX_VMCS_ENUM[9:1] to read and
write all VMCS fields may omit one field.
Workaround: None identified.
Status: For the Steppings affected, see the Summary Tables of Changes.