User Manual

Intel® Xeon® Processor E5-2600 v4 Product Family 21
Specification Update December 2016
Implication: Due to this erratum, when using low SAV values, the program may get incorrect PEBS
or PMI interrupts and/or an invalid counter state.
Workaround: The sampling driver should avoid using SAV<100.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF20 CR0.CD Is Ignored in VMX Operation
Problem: If CR0.CD=1, the MTRRs and PAT should be ignored and the UC memory type should be
used for all memory accesses. Due to this erratum, a logical processor in VMX
operation will operate as if CR0.CD=0 even if that bit is set to 1.
Implication: Algorithms that rely on cache disabling may not function properly in VMX operation.
Workaround: Algorithms that rely on cache disabling should not be executed in VMX root operation.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF21 Instruction Fetch May Cause Machine Check if Page Size and Memory
Type Was Changed Without Invalidation
Problem: This erratum may cause a machine-check error (IA32_MCi_STATUS.MCACOD=0150H)
on the fetch of an instruction that crosses a 4-KByte address boundary. It applies only
if (1) the 4-KByte linear region on which the instruction begins is originally translated
using a 4-KByte page with the WB memory type; (2) the paging structures are later
modified so that linear region is translated using a large page (2-MByte, 4-MByte, or 1-
GByte) with the UC memory type; and (3) the instruction fetch occurs after the paging-
structure modification but before software invalidates any TLB entries for the
linear region.
Implication: Due to this erratum an unexpected machine check with error code 0150H may occur,
possibly resulting in a shutdown. Intel has not observed this erratum with any
commercially available software.
Workaround: Software should not write to a paging-structure entry in a way that would change, for
any linear address, both the page size and the memory type. It can instead use the
following algorithm: first clear the P flag in the relevant paging-structure entry (for
example, PDE); then invalidate any translations for the affected linear addresses; and
then modify the relevant paging-structure entry to set the P flag and establish the new
page size and memory type.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF22 Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value
for VEX.vvvv May Produce a #NM Exception
Problem: The VAESIMC and VAESKEYGENASSIST instructions should produce a #UD (Invalid-
Opcode) exception if the value of the vvvv field in the VEX prefix is not 1111b. Due to
this erratum, if CR0.TS is “1”, the processor may instead produce a #NM (Device-Not-
Available) exception.
Implication: Due to this erratum, some undefined instruction encodings may produce a #NM instead
of a #UD exception.
Workaround: Software should always set the vvvv field of the VEX prefix to 1111b for instances of
the VAESIMC and VAESKEYGENASSIST instructions.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF23 Interrupt From Local APIC Timer May Not Be Detectable While Being
Delivered
Problem: If the local-APIC timer’s CCR (current-count register) is 0, software should be able to
determine whether a previously generated timer interrupt is being delivered by first
reading the delivery-status bit in the LVT timer register and then reading the bit in the
IRR (interrupt-request register) corresponding to the vector in the LVT timer register. If
both values are read as 0, no timer interrupt should be in the process of being
delivered. Due to this erratum, a timer interrupt may be delivered even if the CCR is 0