User Manual

18 Intel® Xeon® Processor E5-2600 v4 Product Family
Specification Update December 2016
BDF6 Unexpected Performance Loss When Turbo Disabled
Problem: When Intel Turbo Boost Technology is disabled by IA32_MISC_ENABLES MSR (416H)
TURBO_MODE_DISABLE bit 38, the Ring operating frequency may be below P1
operating frequency.
Implication: Processor performance may be below expectations for P1 operating frequency.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF7 Attempting to Enter ADR May Lead to Unpredictable System Behavior
Problem: Due to this erratum, an attempt to transition the memory subsystem to ADR
(Asynchronous DRAM Self Refresh) mode may fail.
Implication: This erratum may lead to unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF8 Exiting From Package C3 or Package C6 With DDR4-2133 May Lead to
Unpredictable System Behavior
Problem: Due to this erratum, with DDR4-2133 memory, exiting from PC3 (package C3) or PC6
(package C6) state may lead to unpredictable system behavior.
Implication: This erratum may lead to unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF9 The System May Shut Down Unexpectedly During a Warm Reset
Problem: Certain complex internal timing conditions present when a warm reset is requested can
prevent the orderly completion of in-flight transactions. It is possible under these
conditions that the warm reset will fail and trigger a full system shutdown.
Implication: When this erratum occurs, the system will shut down and all machine check error logs
will be lost.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF10 CAT May Not Behave as Expected
Problem: Due to this erratum, CAT (Cache Allocation Technology) way enforcement may not
behave as configured.
Implication: When this erratum occurs, cache quality of service guarantees may not be met.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the Steppings affected, see the Summary Tables of Changes.
BDF11 LBR, BTS, BTM May Report a Wrong Address when an Exception/
Interrupt Occurs in 64-bit Mode
Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record),
BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However,
during a specific boundary condition where the exception/interrupt occurs right after
the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF)
in 64-bit mode, the LBR return registers will save a wrong return address with bits 63
to 48 incorrectly sign extended to all 1’s. Subsequent BTS and BTM operations which
report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an
exception/interrupt.