Intel® Xeon® Processor E5-2600 v4 Product Family Specification Update December 2016 Reference Number: 333811-002US
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Contents Preface ...................................................................................................................... 5 Identification Information ......................................................................................... 6 Microcode Updates .................................................................................................. 12 Summary Tables of Changes....................................................................................
Revision History Revision 001 002 Description • Initial Release • • • • • Date May 2015 December 2016 Updated Microcode Table Updated Table 1 and Table 2 Added Table 5 Removed BDF42 and BDF61 Added BDF64 - BDF85 § 4 Intel® Xeon® Processor E5-2600 v4 Product Family Specification Update December 2016
Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
Identification Information Component Identification via Programming Interface The Intel® Xeon® Processor E5-2600 v4 Product Family Stepping can be identified by the following register contents: Reserved Extended Family1 Extended Model2 Reserved Processor Type3 Family Code4 Model Number5 Stepping ID6 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0 00000000b 0100b 00b 0110b 1111b varies per stepping Notes: 1.
Component Marking Information Figure 1. Intel® Xeon® Processor E5-2600 v4 Product FamilyTop-side Markings (Example) The Intel® Xeon® Processor E5-2600 v4 Product Family stepping can be identified by the following component markings. Refer to the Dear Customer Letter (DCL) for additional details and conditions of test support. Table 1.
Table 1. Intel® Xeon® Processor E5-2600 v4 Product Family Identification (Sheet 2 of 2) Spec Sequential Number Stepping FG MM# S-Spec Core frequency (GHz) TDP (W) Number of Cores DDR4 Frequency (MHz) Last Level Cache Size (MB) E5-2603V4 R0 948124 SR2P0 1.7 85 6 1866 15 E5-2609V4 R0 948125 SR2P1 1.7 85 8 1866 20 E5-2699AV4 B0 952190 SR30Y 2.4 145 22 2400 55 E5-2679V4 B0 946688 SR2K5 2.5 200 20 2400 50 E5-2699AV4 B0 952190 SR30Y 2.
Table 3. Intel® Xeon® Processor E5-2600 v4 Product Family Identification. Q - Spec and stepping summary (Sheet 2 of 2) Spec Sequential Number Q-Spec Stepping CPUID Core frequency (GHz) TDP (W) Number of cores Last Level Cache Size (MB) E5-2648LV4 QK9C M0 0x406F1 2.5 75 14 35 E5-2650LV4 QK93 M0 0x406F1 2.5 65 14 35 E5-2687WV4 QK99 M0 0x406F1 3.5 160 12 30 E5-2660V4 QK90 M0 0x406F1 3.3 105 12 30 E5-2650V4 QK8Y M0 0x406F1 2.
Table 4. Spec Sequential Number Stepping FG MM# S-Spec Core frequency (GHz) TDP (W) Number of Cores Last Level Cache Size (MB) E5-4655 v4 QKSX M0 0x406F1 3.2 135 8 30 E5-4610 v4 QKSU M0 0x406F1 1.8 105 10 25 E5-4627 v4 QKSZ M0 0x406F1 2.6 135 10 25 E5-4620 v4 QKSY M0 0x406F1 2.6 105 10 25 E5-4640 v4 QKSS M0 0x406F1 2.6 105 12 30 E5-4650 v4 QKSQ M0 0x406F1 2.
Intel® Xeon® Processor E5-2600 v4 Product Family Identification Turbo Bins Model Number TDP (W) # Cores Intel® Turbo Boost Technology Maximum Core Frequency (GHz) Stepping Table 5. SR2NC M0 E5-2628LV4 75 15 2.4 2.2 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 1,2,3,8 SR2P9 R0 E5-2608LV4 50 10 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1,2,3,5,7,8 S-Spec No Notes Core 1 -2 Core 3 Core 4 Core 5 Core 6 Core 7 Core 8 Core 9 Core 10 Core 11+ SR2PE R0 E5-2618LV4 75 10 3.
Microcode Updates Each unique processor stepping/package combination has an associated microcode update that, when applied, constitutes a supported processor (that is, Specified Processor = Processor Stepping + Microcode Update). The proper microcode update must be loaded on each processor in a system. The proper microcode update is defined as the latest microcode update available from Intel for a given family, model and stepping of the processor.
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Product Name product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations: Codes Used in Summary Tables Stepping X: Errata exists in the stepping indicated.
Table 1.
Table 1. Integrated Core/Uncore Errata (Sheet 3 of 4) Steppings Number Status ERRATA B0/M0/R0 BDF41 X No Fix Reading The Memory Destination of an Instruction That Begins an HLE Transaction May Return The Original Value BDF42 X No Fix Removed. BDF43 X No Fix Performance Monitoring Event INSTR_RETIRED.
Table 1.
Integrated Core/Uncore Errata BDF1 Enabling ISOCH Mode May Cause The System to Hang Problem: When ISOCH (Isochronous) operation is enabled within BIOS, the system may hang and fail to boot. Implication: Due to this erratum, the system may hang and fail to boot. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the Steppings affected, see the Summary Tables of Changes.
BDF6 Unexpected Performance Loss When Turbo Disabled Problem: When Intel Turbo Boost Technology is disabled by IA32_MISC_ENABLES MSR (416H) TURBO_MODE_DISABLE bit 38, the Ring operating frequency may be below P1 operating frequency. Implication: Processor performance may be below expectations for P1 operating frequency. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the Steppings affected, see the Summary Tables of Changes.
Workaround: None identified. Status: For the Steppings affected, see the Summary Tables of Changes. BDF12 EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change Problem: EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change Problem: This erratum is regarding the case where paging structures are modified to change a linear address from writable to non-writable without software performing an appropriate TLB invalidation.
linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially available software. Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space. Status: For the Steppings affected, see the Summary Tables of Changes.
Implication: Due to this erratum, when using low SAV values, the program may get incorrect PEBS or PMI interrupts and/or an invalid counter state. Workaround: The sampling driver should avoid using SAV<100. Status: For the Steppings affected, see the Summary Tables of Changes. BDF20 CR0.CD Is Ignored in VMX Operation Problem: If CR0.CD=1, the MTRRs and PAT should be ignored and the UC memory type should be used for all memory accesses.
and the LVT and IRR bits are read as 0. This can occur only if the DCR (Divide Configuration Register) is greater than or equal to 4. The erratum does not occur if software writes zero to the Initial Count Register before reading the LVT and IRR bits. Implication: Software that relies on reads of the LVT and IRR bits to determine whether a timer interrupt is being delivered may not operate properly.
other processor thread does not have on demand clock modulation enabled and that thread is executing a stream of instructions with the lock prefix that either split a cacheline or access UC memory. Implication: Program execution may stall on both threads of the core subject to this erratum. Workaround: This erratum will not occur if clock modulation is enabled on all threads when using on demand clock modulation or if the duty cycle programmed in the IA32_CLOCK_MODULATION MSR is 18.75% or higher.
BDF32 Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be Observed Problem: During RTM (Restricted Transactional Memory) operation when branch tracing is enabled using BTM (Branch Trace Message) or BTS (Branch Trace Store), the incorrect EIP value (From_IP pointer) may be observed for an RTM abort. Implication: Due to this erratum, the From_IP pointer may be the same as that of the immediately preceding taken branch. Workaround: None identified.
BDF37 VM Exit May Set IA32_EFER.NXE When IA32_MISC_ENABLE Bit 34 is Set to 1 Problem: When “XD Bit Disable” in the IA32_MISC_ENABLE MSR (1A0H) bit 34 is set to 1, it should not be possible to enable the “execute disable” feature by setting IA32_EFER.NXE. Due to this erratum, a VM exit that occurs with the 1-setting of the “load IA32_EFER” VM-exit control may set IA32_EFER.NXE even if IA32_MISC_ENABLE bit 34 is set to 1.
memory destination of that instruction may return the value that was in memory before the transactional region began. Implication: Due to this erratum, unpredictable system behavior may occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the Steppings affected, see the Summary Tables of Changes. BDF42 Removed. BDF43 Performance Monitoring Event INSTR_RETIRED.
Status: For the Steppings affected, see the Summary Tables of Changes. BDF47 General-Purpose Performance Counters May be Inaccurate with Any Thread Problem: The IA32_PMCx MSR (C1H - C8H) general-purpose performance counters may report inaccurate counts when the associated event selection IA32_PERFEVTSELx MSR’s (186H - 18DH) AnyThread field (bit 21) is set and either. Implication: Due to this erratum, IA32_PMCx counters may be inaccurate. Workaround: None identified.
BDF52 Processor Does Not Check IRTE Reserved Bits Problem: As per the Intel® Virtualization Technology for Directed I/O (Intel® VT-d) specification, bits 63:HAW (Host Address Width) of the Posted Interrupt Descriptor Upper Address field in the IRTE (Interrupt Remapping Table Entry) must be checked for a value of 0; violations must be reported as an interrupt-remapping fault. Due to this erratum, hardware does not perform this check and does not signal an interrupt-remapping fault on violations.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the Steppings affected, see the Summary Tables of Changes. BDF57 Writing MSR_ERROR_CONTROL May Cause a #GP Problem: A WRMSR that attempts to set MODE1_MEMERROR_REPORT field (bit 1) and/or MEM_CORRERR_LOGGING_DISABLE field (bit 5) of the MSR_ERROR_CONTROL MSR (17FH) may incorrectly cause a #GP (General Protection exception).
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the Steppings affected, see the Summary Tables of Changes. BDF63 A #VE May Not Invalidate Cached Translation Information Problem: An EPT (Extended Page Table) violation that causes a #VE (virtualization exception) may not invalidate the guest-physical mappings that were used to translate the guestphysical address that caused the EPT violation. Implication: Due to this erratum, the system may hang.
BDF68 PEBS Record May Be Generated After Being Disabled Problem: A performance monitoring counter may generate a PEBS (Precise Event Based Sampling) record after disabling PEBS or the performance monitoring counter by clearing the corresponding enable bit in IA32_PEBS_ENABLE MSR (3F1H) or IA32_PERF_GLOBAL_CTRL MSR (38FH). Implication: A PEBS record generated after a VMX transition will store into memory according to the post-transition DS (Debug Store) configuration.
BDF73 Internal Parity Errors May Incorrectly Report Overflow in the IA32_MC0_STATUS MSR Problem: Due to this erratum, an uncorrectable internal parity error with an IA32_MC0_STATUS.MCACOD (bits [15:0]) value of 0005H may incorrectly set the IA32_MC0_STATUS.OVER flag (bit 62) indicating an overflow when a single error has been observed. Implication: IA32_MC0_STATUS.OVER may not accurately indicate multiple occurrences of errors. There is no other impact to normal processor functionality.
Implication: When this erratum occurs, performance may be reduced, concurrent with an incorrect assertion of the PROCHOT# signal. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the Steppings affected, see the Summary Tables of Changes. BDF78 Writing The IIO_LLC_WAYS MSR Results in an Incorrect Value Problem: Writing the IIO_LLC_WAYS MSR (C8Bh) always sets bits [1:0] regardless of the value written.
MEM_HOT_C23_N signal as an input to throttle DIMM activity as needed. See Grantley Platform Design Guide Rev. 2.2, IBL ID: 506549 for further details. Status: For the Steppings affected, see the Summary Tables of Changes. BDF83 Bi-Directional PCIe* Posted Transactions May Lead to System Hang Problem: Certain bi-directional PCIe posted traffic patterns between CPU nodes may lead to a loss of flow control credits resulting in a link hang.
