Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet - Volume One May 2012 Reference Number: 326508, Revision: 002
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Contents 1 Overview ................................................................................................................. 13 1.1 Introduction ..................................................................................................... 13 1.1.1 Processor Feature Details ........................................................................ 14 1.1.2 Supported Technologies .......................................................................... 14 1.2 Interfaces ......................
3.3 3.4 3.5 3.6 3.7 3.8 3.2.4 Execute Disable Bit .................................................................................83 Intel® Hyper-Threading Technology .....................................................................83 Intel® Turbo Boost Technology ...........................................................................83 3.4.1 Intel® Turbo Boost Operating Frequency ...................................................83 Enhanced Intel SpeedStep® Technology ...........................
7 Electrical Specifications ......................................................................................... 151 7.1 Processor Signaling ......................................................................................... 151 7.1.1 System Memory Interface Signal Groups ................................................. 151 7.1.2 PCI Express* Signals ............................................................................ 151 7.1.3 DMI2/PCI Express* Signals..................................
Figures 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 2-33 2-34 2-35 2-36 2-37 2-38 2-39 2-40 2-41 2-42 2-43 2-44 2-45 2-46 6 Intel® Xeon® Processor E5-2600 Product Family on the 2 Socket Platform ...........................................................................................................14 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)...................
2-47 2-48 2-49 2-50 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 RdPCIConfigLocal()............................................................................................ 66 WrPCIConfigLocal() ........................................................................................... 68 The Processor PECI Power-up Timeline() ........................................
10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 STS200C Passive/Active Combination Heat Sink (with Removable Fan) ................... 244 STS200C Passive/Active Combination Heat Sink (with Fan Removed)...................... 244 STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks ................................ 245 Boxed Processor Motherboard Keepout Zones (1 of 4) .......................................... 246 Boxed Processor Motherboard Keepout Zones (2 of 4) ...........................
4-10 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 7-1 7-2 7-3 7-4 7-5 7-6 7-7 Package C-State Power Specifications .................................................................. 97 Processor SKU Summary Table .........................................................................
7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 8-1 8-2 9-1 9-2 9-3 10-1 10-2 10-3 10 Fault Resilient Booting (Output Tri-State) Signals ................................................. 163 Processor Absolute Minimum and Maximum Ratings ............................................. 164 Storage Condition Ratings................................................................................. 165 Voltage Specification .................................................
Revision History Revision Number Description Revision Date 001 Initial Release March 2012 002 Added Intel® Xeon® Processor E5-4600 Product Family May 2012 § Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One 11
Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One
Overview 1 Overview 1.1 Introduction The Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One provides DC specifications, signal integrity, differential signaling specifications, land and signal definitions, and an overview of additional processor feature interfaces. The Intel® Xeon® processor E5-1600/E5-2600/E5-4600 product families are the next generation of 64-bit, multi-core enterprise processors built on 32-nanometer process technology.
Overview Figure 1-1. Intel® Xeon® Processor E5-2600 Product Family on the 2 Socket Platform Figure 1-2. Intel® Xeon® Processor E5-4600 Product Family on the 4 Socket Platform 1.1.
Overview • 46-bit physical addressing and 48-bit virtual addressing • 1 GB large page support for server applications • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data mid-level (L2) cache for each core • Up to 20 MB last level cache (LLC): up to 2.
Overview — UDIMMs x8, x16 — RDIMMs x4, x8 — LRDIMM x4, x8 (2-Gb and 4-Gb only) • Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM • Open with adaptive idle page close timer or closed page policy • Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern • Isochronous access support for Quality of Service (QoS), native 1 and 2 socket platforms - Intel® Xeon® processor E5-1600 an
Overview — x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1. — x8 port (Port 1) may negotiate down to x4, x2, or x1. — x4 port (Port 0) may negotiate down to x2, or x1. — When negotiating down to narrower widths, there are caveats as to how lane reversal is supported. • Non-Transparent Bridge (NTB) is supported by PCIe* Port3a/IOU1. For more details on NTB mode operation refer to PCI Express Base Specification - Revision 3.0: — x4 or x8 widths and at PCIe* 1.0, 2.0, 3.
Overview Figure 1-3. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) Port 0 DMI / PCIe Transaction Link Physical Port 1 (IOU2) PCIe Port 2 (IOU0) PCIe Transaction Port 3 (IOU1) PCIe Transaction Link Transaction Link Physical Link Physical Physical 0…3 0…3 4…7 0…3 4…7 8…11 12..15 0…3 4…7 8…11 12..
Overview • Home snoop based coherency • 3-bit Node ID • 46-bit physical addressing support • No Intel QuickPath Interconnect bifurcation support • Differential signaling • Forwarded clocking • Up to 8.
Overview • Memory thermal monitoring via MEM_HOT_C01_N and MEM_HOT_C23_N Signals 1.3.4 PCI Express • L0s is not supported • L1 ASPM power management capability 1.3.5 Intel QuickPath Interconnect • L0s is not supported • L0p and L1 power management capabilities 1.
Overview Term Description Enhanced Intel SpeedStep® Technology Allows the operating system to reduce power consumption when performance is not needed. Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system.
Overview Term 22 Description LLC Last Level Cache LRDIMM Load Reduced Dual In-line Memory Module NCTF Non-Critical to Function: NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. NEBS Network Equipment Building System. NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States.
Overview Term 1.7 Description TDP Thermal Design Power TSOD Thermal Sensor on DIMM UDIMM Unbuffered Dual In-line Module Uncore The portion of the processor comprising the shared cache, IMC, HA, PCU, UBox, and Intel QPI link interface. Unit Interval Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If a number of edges are collected at instances t1, t2, tn,....
Overview Table 1-1. Referenced Documents (Sheet 2 of 2) Document 1.8 Location Intel® Virtualization Technology Specification for Directed I/O Architecture Specification http://download.intel.com/technolog y/computing/vptech/Intel(r)_VT_for_ Direct_IO.pdf Intel® Trusted Execution Technology Software Development Guide http://www.intel.com/technology/sec urity/ State of Data The data contained within this document is the most accurate information available by the publication date of this document.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels with 8 bits of ECC for each channel (total of 72-bits) and supports 1 to 3 DIMMs per channel depending on the type of memory installed.
Interfaces 2.2 PCI Express* Interface This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0. 2.2.1 PCI Express* Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.
Interfaces Figure 2-2. Packet Flow through the Layers Framing Sequence Number Header Data ECRC LCRC Framing Transaction Layer Data Link Layer Physical Layer 2.2.1.1 Transaction Layer The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events.
Interfaces 256 bytes of a logical device's configuration space) and an extended PCI Express* region (which consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express* configuration access mechanism described in the PCI Express* Enhanced Configuration Mechanism section.
Interfaces optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture. The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional links to complete the connection between two components.
2.5 Platform Environment Control Interface (PECI) The Platform Environment Control Interface (PECI) uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic ‘0’ or logic ‘1’.
2.5.1.1 Thermal Management Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS) thermal readings acquired via PECI against the processor-specific fan speed control reference point, or TCONTROL. Both TCONTROL and DTS thermal readings are accessible via the processor PECI client. These variables are referenced to a common temperature, the TCC activation point, and are both defined as negative offsets from that reference.
Figure 2-3. Ping() Byte # Byte Definition 0 1 2 3 Client Address Write Length 0x00 Read Length 0x00 FCS An example Ping() command to PECI device address 0x30 is shown below. Figure 2-4. Ping() Example Byte # Byte Definition 2.5.2.2 0 1 2 3 0x30 0x00 0x00 0xe1 GetDIB() The processor PECI client implementation of GetDIB() includes an 8-byte response and provides information regarding client revision number and the number of supported domains.
2.5.2.2.2 Device Info The Device Info byte gives details regarding the PECI client configuration. At a minimum, all clients supporting GetDIB will return the number of domains inside the package via this field. With any client, at least one domain (Domain 0) must exist. Therefore, the Number of Domains reported is defined as the number of domains in addition to Domain 0. For example, if bit 2 of the Device Info byte returns a ‘1’, that would indicate that the PECI client supports two domains. Figure 2-6.
Table 2-2. Minor Revision Number Meaning Minor Revision Supported Command Suite 5 Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig(), WrPCIConfig() 6 Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(), RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig(), WrPCIConfig(), WrIAMSR() For the processor PECI client the Revision Number will return ‘0011 0100b’. 2.5.2.
Example bus transaction for a thermal sensor device located at address 0x30 returning a value of negative 10 counts is show in Figure 2-9. Figure 2-9. GetTemp() Example Byte # Byte Definition 2.5.2.3.2 0 1 2 3 0x30 0x01 0x02 0x01 4 5 6 7 0xef 0x80 0xfd 0x4b Supported Responses The typical client response is a passing FCS and valid thermal data. Under some conditions, the client’s response will indicate a failure. GetTemp() response definitions are listed in Table 2-3. Refer to Section 2.
processor PECI clients. All command responses are prepended with a completion code that contains additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes. Figure 2-10. RdPkgConfig() Note: The 2-byte parameter field and 4-byte read data field defined in Figure 2-10 are sent in standard PECI ordering with LSB first and MSB last. 2.5.2.4.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data.
Read Length: 0x01 Command: 0xa5 AW FCS Support: Yes Description: Writes data to the processor PCS entry as specified by the ‘index’ and ‘parameter’ fields. This command supports only dword data writes on the processor PECI clients. All command responses include a completion code that provides additional pass/fail status information. Refer to Section 2.5.5.2 for details regarding completion codes.
Table 2-5. WrPkgConfig() Response Definition (Sheet 2 of 2) Response 2.5.2.6 Meaning CC: 0x80 Response timeout. The processor was not able to generate the required response in a timely fashion. Retry is appropriate. CC: 0x81 Response timeout. The processor is not able to allocate resources for servicing this command at this time. Retry is appropriate. CC: 0x90 Unknown/Invalid/Illegal Request CC: 0x91 PECI control hardware, firmware or associated logic error.
Table 2-6.
Table 2-6.
2.5.2.6.3 DRAM Rank Temperature Write This feature allows the PECI host to program into the processor, the temperature for all the ranks within a DIMM up to a maximum of four ranks as shown in Figure 2-13. The DIMM index and Channel index are specified through the parameter field as shown in Table 2-7.
Figure 2-14. The Processor DIMM Temperature Read / Write 31 24 23 Reserved 16 15 DIMM# 2 Absolute Temp (in Degrees C) 8 7 DIMM# 1 Absolute Temp (in Degrees C) 0 DIMM# 0 Absolute Temp (in Degrees C) DIMM Temperature Data 15 3 Reserved 2 0 Channel Index Parameter format 2.5.2.6.5 DIMM Ambient Temperature Write / Read This feature allows the PECI host to provide an ambient temperature reference to be used by the processor for activity-based DRAM temperature estimation.
Figure 2-16. Processor DRAM Channel Temperature 31 24 23 Channel 3 Maximum Temperature (in Degrees C) 16 15 Channel 2 Maximum Temperature (in Degrees C) 8 7 Channel 1 Maximum Temperature (in Degrees C) 0 Channel 0 Maximum Temperature (in Degrees C) Channel Temperature Data 2.5.2.6.7 Accumulated DRAM Energy Read This feature allows the PECI host to read the DRAM energy consumed by all the DIMMs within all the channels or all the DIMMs within just a specified channel.
The minimum DRAM power in Figure 2-18 corresponds to a minimum bandwidth setting of the memory interface. It does ‘not’ correspond to a processor IDLE or memory self-refresh state. The ‘time window’ in Figure 2-18 is representative of the rate at which the power control unit (PCU) samples the DRAM energy consumption information and reactively takes the necessary measures to meet the imposed power limits.
The following conversion formula should be used for encoding or programming the ‘Control Time Window’ in bits [23:17]. Control Time Window (in seconds) = ([1 + 0.25 * ‘x’] * 2‘y’) * ‘z’ where ‘x’ = integer value of bits[23:22] ‘y’ = integer value of bits[21:17] ‘z’ = Package Power SKU Time Unit[19:16] (see Section 2.5.2.6.13 for details on Package Power SKU Unit) For example, using this formula, a control time value of 0x0A will correspond to a ‘1-second’ time window.
2.5.2.6.11 CPU Thermal and Power Optimization Capabilities Table 2-8 provides a summary of the processor power and thermal optimization capabilities that can be accessed over PECI. Note: The Index values referenced in Table 2-8 are in decimal format. Table 2-8 also provides information on alternate inband mechanisms to access similar or equivalent information for register reads and writes where applicable.
Table 2-8. Service RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 2 of 3) Parameter RdPkgConfig() Index WrPkgConfig() Value Value Data (dword) Data (dword) (decimal) (word) Description Alternate Inband MSR or CSR Access “Wake on PECI” Mode Bit Write / Read 05 0x0000 “Wake on PECI” mode bit N/A Read status of “Wake on PECI” mode bit Accumulated Run Time Read 31 0x0000 Total reference time N/A Returns the total run time.
Table 2-8.
2.5.2.6.12 Package Identifier Read This feature enables the PECI host to uniquely identify the PECI client processor. The parameter field encodings shown in Table 2-8 allow the PECI host to access the relevant processor information as described below. • CPUID data: This is the equivalent of data that can be accessed through the CPUID instruction execution. It contains processor type, stepping, model and family ID information as shown in Figure 2-21. Figure 2-21.
Figure 2-24. Maximum Thread ID 31 4 3 0 Max Thread ID Reserved Maximum Thread ID Data • CPU Microcode Update Revision: Reflects the revision number for the microcode update and power control unit firmware updates on the processor sample. The revision data is a unique 32-bit identifier that reflects a combination of specific versions of the processor microcode and PCU control firmware. Figure 2-25.
Table 2-9. Power Control Register Unit Calculations Unit Field Time 2.5.2.6.14 Value Calculation 1s / 2TIME UNIT Energy 1J / 2ENERGY UNIT Power POWER UNIT 1W / 2 Default Value 1s / 210 = 976 µs 1J / 216 = 15.3 µJ 1W / 23 = 1/8 W Package Power SKU Read This read allows the PECI host to access the minimum, Thermal Design Power and maximum power settings for the processor package SKU. It also returns the maximum time interval or window over which the power can be sustained.
Figure 2-28. Package Power SKU Data 63 55 54 48 47 Maximum Time Window Reserved 46 Reserved 32 Maximum Package Power Package Power SKU (upper bits) 31 30 Reserved 16 Minimum Package Power 15 14 Reserved 0 TDP Package Power Package Power SKU (lower bits) 2.5.2.6.
2.5.2.6.18 Per Core DTS Temperature Read This feature enables the PECI host to read the maximum value of the DTS temperature for any specific core within the processor. Alternatively, this service can be used to read the System Agent temperature. Temperature is returned in the same format as the Package Temperature Read described in Section 2.5.2.6.17. Data is returned in relative PECI temperature format.
Figure 2-31. Thermal Status Word 31 6 5 4 3 2 1 0 Reserved Critical Temperature Log Critical Temperature Status Bidirectional PROCHOT# Log Bidirectional PROCHOT# Status TCC Activation Log TCC Activation Status 2.5.2.6.21 Thermal Averaging Constant Write / Read This feature allows the PECI host to control the window over which the estimated processor PECI temperature is filtered. The host may configure this window as a power of two.
Figure 2-33. Current Config Limit Read Data 31 13 12 RESERVED 0 Current Limit for processor VCC Current Config Limit Data 2.5.2.6.24 Accumulated Energy Status Read This service can return the value of the total energy consumed by the entire processor package or just the logic supplied by the VCC power plane as specified through the parameter field in Table 2-8. This information is tracked by a 32-bit counter that wraps around and continues counting on reaching its limit.
compared to the input PROCHOT_N signal assertion method. Both power limit enabling and initialization of power limit values can be done in the same command cycle. Setting a power limit for the VCC plane enables turbo modes for associated logic. External VR protection is guaranteed during boot through operation at safe voltage and frequency.
‘Power Limit 1’ values may be impacted by the processor heat sinks and system air flow. Processor ‘power limit 2’ can be used as appropriate to limit the current drawn by the processor to prevent any external power supply unit issues. The ‘Power Limit 2’ should always be programmed to a value (typically 20%) higher than ‘Power Limit 1’ and has no default value associated with it.
2.5.2.6.28 Efficient Performance Indicator Read The Efficient Performance Indicator (EPI) Read provides an indication of the total number of productive cycles. Specifically, these are the cycles when the processor is engaged in any activity to retire instructions and as a result, consuming energy. Any power management entity monitoring this indicator should sample it at least once every 4 seconds to enable detection of wraparounds.
2.5.2.6.30 Caching Agent TOR Read This feature allows the PECI host to read the Caching Agent (Cbo) Table of Requests (TOR). This information is useful for debug in the event of a 3-strike timeout that results in a processor IERR assertion. The 16-bit parameter field is used to specify the Cbo index, TOR array index and bank number according to the following bit assignments.
2.5.2.7 RdIAMSR() The RdIAMSR() PECI command provides read access to Model Specific Registers (MSRs) defined in the processor’s Intel® Architecture (IA). MSR definitions may be found in the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3. Refer to Table 2-11 for the exact listing of processor registers accessible through this command. 2.5.2.7.
Figure 2-42. Processor ID Construction Example Cores 0,1.2...7 C7 T1 C6 C5 C4 C3 C2 C1 C0 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 T0 0 Processor ID (0..15) Thread (0,1) Mask for Core4 Figure 2-43. RdIAMSR() Note: The 2-byte MSR Address field and read data field defined in Figure 2-43 are sent in standard PECI ordering with LSB first and MSB last.
2.5.2.7.3 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. Table 2-10. RdIAMSR() Response Definition Response Bad FCS 2.5.2.7.4 Meaning Electrical error Abort FCS Illegal command formatting (mismatched RL/WL/Command Code) CC: 0x40 Command passed, data is valid. CC: 0x80 Response timeout. The processor was not able to generate the required response in a timely fashion.
Table 2-11.
2.5.2.8 RdPCIConfig() The RdPCIConfig() command provides sideband read access to the PCI configuration space maintained in downstream devices external to the processor. PECI originators may conduct a device/function/register enumeration sweep of this space by issuing reads in the same manner that the BIOS would. A response of all 1’s may indicate that the device/function/register is unimplemented even with a ‘passing’ completion code.
2.5.2.8.2 Supported Responses The typical client response is a passing FCS, a passing Completion Code and valid data. Under some conditions, the client’s response will indicate a failure. The PECI client response can also vary depending on the address and data. It will respond with a passing completion code if it successfully submits the request to the appropriate location and gets a response. Table 2-12. RdPCIConfig() Response Definition Response Bad FCS Abort FCS 2.5.2.
2.5.2.9.1 Command Format The RdPCIConfigLocal() format is as follows: Write Length: 0x05 Read Length: 0x02 (byte), 0x03 (word), 0x05 (dword) Command: 0xe1 Description: Returns the data maintained in the PCI configuration space within the processor at the requested PCI configuration address. The Read Length dictates the desired data return size. This command supports byte, word and dword responses as well as a completion code.
Table 2-13. RdPCIConfigLocal() Response Definition (Sheet 2 of 2) Response 2.5.2.10 Meaning CC: 0x82 The processor hardware resources required to service this command are in a low power state. Retry may be appropriate after modification of PECI wake mode behavior if appropriate. CC: 0x90 Unknown/Invalid/Illegal Request CC: 0x91 PECI control hardware, firmware or associated logic error. The processor is unable to process the request.
Figure 2-48. WrPCIConfigLocal() Byte # Byte Definition 0 1 2 3 Client Address Write Length {0x07, 0x08, 0x0a} Read Length 0x01 Cmd Code 0xe5 4 Host ID[7:1] & Retry[0] 8 LSB Note: 5 LSB 6 PCI Configuration Address 9 10 7 MSB 11 Data (1, 2 or 4 bytes) MSB 12 13 14 15 AW FCS FCS Completion Code FCS The 3-byte PCI configuration address and write data field defined in Figure 2-48 are sent in standard PECI ordering with LSB first and MSB last. 2.5.2.10.
2.5.2.10.3 WrPCIConfigLocal() Capabilities On the processor PECI clients, the PECI WrPCIConfigLocal() command provides a method for programming certain integrated memory controller and IIO functions as described in Table 2-15. Refer to the Intel® Xeon® Processor E5 Product Family Datasheet Volume Two for more details on specific register definitions. It also enables writing to processor REUT (Robust Electrical Unified Test) registers associated with the Intel QPI, PCIe* and DDR3 functions. Table 2-15.
Table 2-16.
The client address may not be changed after PWRGOOD assertion, until the next power cycle on the processor. Removal of a processor from its socket or tri-stating a processor will have no impact to the remaining non-tri-stated PECI client addresses. Since each socket in the system should have a unique PECI address, the SOCKET_ID strapping is required to be unique for each socket. Table 2-17. SOCKET ID Strapping 2.5.3.
2.5.3.5 S-states The processor PECI client is always guaranteed to be operational in the S0 sleep state. • The Ping(), GetDIB(), GetTemp(), RdPkgConfig(), WrPkgConfig(), RdPCIConfigLocal() and WrPCIConfigLocal() will be fully operational in S0 and S1. Responses in S3 or deeper states are dependent on POWERGOOD assertion status. • The RdPCIConfig() and RdIAMSR() responses are guaranteed in S0 only. Behavior in S1 or deeper states is indeterminate.
2.5.3.7.2 Link Init Mode In cases where the socket is not one Intel QPI hop away from the Firmware Agent socket, or a working link to the Firmware Agent socket cannot be resolved, the socket is placed in Link Init mode. The socket performs a minimal amount of internal configuration and waits for complete configuration by BIOS. 2.5.3.8 Processor Error Handling Availability of PECI services may be affected by the processor PECI client error status.
2.5.3.10 Enumerating PECI Client Capabilities The PECI host originator should be designed to support all optional but desirable features from all processors of interest. Each feature has a discovery method and response code that indicates availability on the destination PECI client. The first step in the enumeration process would be for the PECI host to confirm the Revision Number through the use of the GetDIB() command.
2.5.5 Client Responses 2.5.5.1 Abort FCS The Client responds with an Abort FCS under the following conditions: • The decoded command is not understood or not supported on this processor (this includes good command codes with bad Read Length or Write Length bytes). • Assured Write FCS (AW FCS) failure. Under most circumstances, an Assured Write failure will appear as a bad FCS.
2.5.6 Originator Responses The simplest policy that an originator may employ in response to receipt of a failing completion code is to retry the request. However, certain completion codes or FCS responses are indicative of an error in command encoding and a retry will not result in a different response from the client. Furthermore, the message originator must have a response policy in the event of successive failure responses. Refer to Table 2-22 for originator response guidelines.
Temperature readings from the processor are always negative in a 2’s complement format, and imply an offset from the processor Tjmax (PECI = 0). For example, if the processor Tjmax is 100°C, a PECI thermal reading of -10 implies that the processor is running at approximately 10°C below Tjmax or at 90°C. PECI temperature readings are not reliable at temperatures above Tjmax since the processor is outside its operating range and hence, PECI temperature readings are never positive.
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One
Technologies 3 Technologies 3.1 Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.
Technologies 3.1.
Technologies — Support for fault collapsing based on Requester ID • Support for both leaf and non-leaf caching • Support for boot protection of default page table — Support for non-caching of invalid page table entries • Support for hardware based flushing of translated but pending writes and pending reads upon IOTLB invalidation. • Support for page-selective IOTLB invalidation.
Technologies These extensions enhance two areas: • The launching of the Measured Launched Environment (MLE). • The protection of the MLE from potential corruption. The enhanced platform provides these launch and control interfaces using Safer Mode Extensions (SMX). The SMX interface includes the following functions: • Measured/Verified launch of the MLE. • Mechanisms to ensure the above measurement is protected and stored in a secure location.
Technologies 3.2.4 Execute Disable Bit Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system. • Allows the processor to classify areas in memory by where application code can execute and where it cannot. • When a malicious worm attempts to insert code in the buffer, the processor disables code execution, preventing damage and worm propagation. 3.
Technologies 3.5 Enhanced Intel SpeedStep® Technology The processor supports Enhanced Intel SpeedStep® Technology as an advanced means of enabling very high performance while also meeting the power-conservation needs of the platform. Enhanced Intel SpeedStep Technology builds upon that architecture using design strategies that include the following: • Separation between Voltage and Frequency Changes.
Technologies The key advantages of Intel AVX are: • Performance - Intel AVX can accelerate application performance via data parallelism and scalable hardware infrastructure across existing and new application domains: — 256-bit vector data sets can be processed up to twice the throughput of 128-bit data sets. — Application performance can scale up with number of hardware threads and number of cores. — Application domain can scale out with advanced platform interconnect fabrics, such as Intel QPI.
Technologies 86 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One
Power Management 4 Power Management This chapter provides information on the following power management topics: • ACPI States • System States • Processor Core/Package States • Integrated Memory Controller (IMC) and System Memory States • Direct Media Interface Gen 2 (DMI2)/PCI Express* Link States • Intel QuickPath Interconnect States 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-1. System States State 4.1.
Power Management Table 4-2.
Power Management Table 4-4. System Memory Power States (Sheet 2 of 2) State Self-Refresh Description CKE de-asserted. In this mode, no transactions are executed and the system memory consumes the minimum possible power. Self refresh modes apply to all memory channels for the processor. • IO-MDLL Off: Option that sets the IO master DLL off when self refresh occurs. • PLL Off: Option that sets the PLL off when self refresh occurs.
Power Management 4.2 Processor Core/Package Power Management While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power C-states have longer entry and exit latencies. 4.2.
Power Management Figure 4-1. Idle Power Management Breakdown of the Processor Cores T h re a d 0 T h re a d 1 T h re a d 0 C o r e 0 S ta te T h re a d 1 C o r e N S ta te P r o c e s s o r P a c k a g e S ta te Figure 4-2.
Power Management For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS. To enable it, refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3. Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read interface.
Power Management A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see Section 4.2.5.2, “Package C1/C1E”. 4.2.4.
Power Management 4.2.5 Package C-States The processor supports C0, C1/C1E, C2, C3, and C6 power states. The following is a summary of the general rules for package C-state entry. These apply to all package C-states unless specified otherwise: • A package C-state request is determined by the lowest numerical core C-state amongst all cores. • A package C-state is automatically resolved by the processor depending on the core idle power states and the status of the platform components.
Power Management Table 4-9. Coordination of Core Power States at the Package Level Core 1 Core 0 Package C-State C0 C1 C3 C6 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C3 C0 C11 C3 C3 C6 C0 C11 C3 C6 Notes: 1. The package C-state will be C1E if all actives cores have resolved a core C1 state or higher. Figure 4-3. Package C-State Entry and Exit C1 C0 C2 C3 4.2.5.1 C6 Package C0 The normal operating state for the processor.
Power Management • At least one core is in the C1 state. • The other cores are in a C1 or lower power state. The package enters the C1E state when: • All cores have directly requested C1E via MWAIT(C1) with a C1E sub-state hint. • All cores are in a power state lower that C1/C1E but the package low power state is limited to C1/C1E via the PMG_CST_CONFIG_CONTROL MSR. • All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is enabled in POWER_CTL.
Power Management • Additional power savings actions, as allowed by the exit latency requirements, include putting Intel QPI and PCIe* links in L1, the uncore is not available, further voltage reduction can be taken. In package C6 state, all cores have saved their architectural state and have had their core voltages reduced to zero volts. The LLC retains context, but no accesses can be made to the LLC in this state, the cores must break out to the internal state package C2 for snoops to occur. 4.2.
Power Management • CKE Power-Down: Opportunistic, per rank control after idle time. There may be different levels. — Active Power-Down. — Precharge Power-Down with Fast Exit. — Precharge power Down with Slow Exit. • Self Refresh: In this mode no transaction is executed. The DDR consumes the minimum possible power. 4.3.1 CKE Power-Down The CKE input land is used to enter and exit different power-down modes. The memory controller has a configurable activity timeout for each rank.
Power Management 4.3.2.3 DLL and PLL Shutdown Self refresh, according to configuration, may be a trigger for master DLL shut-down and PLL shut-down. The master DLL shut-down is issued by the memory controller after the DRAMs have entered self refresh. The PLL shut-down and wake-up is issued by the PCU. The memory controller gets a signal from PLL indicating that the memory controller can start working again. 4.3.3 DRAM I/O Power Management Unused signals are tristated to save power.
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Thermal Management Specifications 5 Thermal Management Specifications 5.1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system, see Section 7.7.1, “Storage Conditions Specifications”. Maintaining the proper thermal environment is key to reliable, long-term system operation.
Thermal Management Specifications The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT_N (see Section 7, “Electrical Specifications”). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed need to guarantee the case temperature meets the thermal profile specifications.
Thermal Management Specifications • TEMPERATURE_TARGET MSR • Tcontrol via PECI - RdPkgConfig() • TDP via PECI - RdPkgConfig() • Core Count - RdPCIConfigLocal() DTS PECI commands will also support DTS temperature data readings. Please see Section 2.5.7, “DTS Temperature Data” for PECI command details. Also, refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for details on DTS based thermal solution design considerations.
Thermal Management Specifications 5.1.3 Processor Thermal Profiles Table 5-1.
Thermal Management Specifications Figure 5-1. Tcase: 8-Core 150W Thermal Profile, Workstation Platform SKU Only Notes: 1. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-3 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation.
Thermal Management Specifications 2. 3. Table 5-3. 106 This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-3 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details.
Thermal Management Specifications 5.1.3.2 8-Core 135W Thermal Specifications Table 5-4. Tcase: 8-Core 135W Thermal Specifications 2U Core Frequency Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes Launch to FMB 135 5 See Figure 5-3 and Table 5-5 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Management Specifications Figure 5-4. DTS: 8-Core 135W Thermal Profile 2U Notes: 1. Some of the processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-5 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation.
Thermal Management Specifications Table 5-5. 8-Core 135W Thermal Profile Table 2U (Sheet 2 of 2) Power (W) Maximum TCASE (°C) Maximum DTS (°C) 80 63.2 72.8 85 64.0 74.2 90 64.8 75.6 95 65.6 77.0 100 66.4 78.4 105 67.2 79.8 110 68.0 81.2 115 68.8 82.6 120 69.6 84.0 125 70.4 85.4 130 71.2 86.8 135 72.0 88.2 5.1.3.3 8/6-Core 130W Thermal Specifications Table 5-6.
Thermal Management Specifications Figure 5-5. Tcase: 8/6-Core 130W Thermal Profile 1U Notes: 1. Please refer to Table 5-7 for discrete points that constitute this thermal profile. 2. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-6. DTS: 8-Core 130W Thermal Profile 1U Notes: 1.
Thermal Management Specifications Figure 5-7. DTS: 6-Core 130W Thermal Profile 1U Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-7 for discrete points that constitute the thermal profile. 3. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Table 5-7.
Thermal Management Specifications Table 5-7. 8/6-Core 130W Thermal Profile Table 1U (Sheet 2 of 2) Maximum TCASE (°C) Power (W) Maximum DTS (°C) 8/6-core 8-core 6-Core 100 78.5 90.0 93.4 105 79.6 91.7 95.2 110 80.7 93.3 97.1 115 81.8 95.0 98.9 120 82.9 96.7 100.7 125 84.0 98.3 102.6 130 85.0 100.0 104.4 5.1.3.4 6-Core 130W 1S WS Thermal Specifications Table 5-8.
Thermal Management Specifications Notes: 1. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-9 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-9.
Thermal Management Specifications Table 5-9. 5.1.3.5 6-Core 130W 1S WS Thermal Profile Table (Sheet 2 of 2) Power (W) Maximum TCASE (°C) Maximum DTS (°C) 85 56.2 68.9 90 57.1 70.5 95 57.9 72.1 100 58.8 73.7 105 59.7 75.3 110 60.5 76.9 115 61.4 78.5 120 62.3 80.1 125 63.1 81.8 130 64.0 83.4 8-Core 115W Thermal Specifications Table 5-10.
Thermal Management Specifications Figure 5-10. Tcase: 8-Core 115W Thermal Profile 1U Notes: 1. Please refer to Table 5-11 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-11. DTS: 8-Core 115W Thermal Profile 1U Notes: 1.
Thermal Management Specifications 3. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Table 5-11. 8-Core 115W Thermal Profile Table 1U 5.1.3.6 Power (W) Maximum TCASE (°C) Maximum DTS (°C) 0 55.0 55.0 5 56.1 56.7 10 57.2 58.3 15 58.3 60.0 20 59.3 61.7 25 60.4 63.3 30 61.5 65.0 35 62.6 66.7 40 63.7 68.3 45 64.8 69.3 50 65.9 71.7 55 66.9 73.3 60 68.
Thermal Management Specifications Figure 5-12. Tcase: 8/6-Core 95W Thermal Profile 1U Notes: 1. Please refer to Table 5-13 for discrete points that constitute this thermal profile. 2. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-13. DTS: 8-Core 95W Thermal Profile 1U Notes: 1.
Thermal Management Specifications Figure 5-14. DTS: 6-Core 95W Thermal Profile 1U Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-13 for discrete points that constitute this thermal profile. 3. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Table 5-13.
Thermal Management Specifications Table 5-13. 8/6-Core 95W Thermal Profile Table 1U (Sheet 2 of 2) Power (W) 5.1.3.7 Maximum TCASE (°C) Maximum DTS (°C) 8/6-core 8-core 6-core 85 70.8 80.6 81.5 90 71.9 82.3 83.3 95 73.0 83.9 85.0 8-Core 70W Thermal Specifications Table 5-14. Tcase: 8-Core 70W Thermal Specifications 1U Core Frequency Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes Launch to FMB 70 5 See Figure 5-15 and Table 5-15 1, 2, 3, 4, 5 Notes: 1.
Thermal Management Specifications Figure 5-16. DTS: 8-Core 70W Thermal Profile 1U Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-15 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation.
Thermal Management Specifications 5.1.3.8 6-Core 60W Thermal Specifications Table 5-16. Tcase: 6-Core 60W Thermal Specifications 1U Core Frequency Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes Launch to FMB 60 5 See Figure 5-17 and Table 5-17 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Management Specifications Figure 5-18. DTS: 6-Core 60W Thermal Profile 1U Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-17 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation.
Thermal Management Specifications 5.1.3.9 4-Core 130W Thermal Specifications Table 5-18. Tcase: 4-Core 130W Thermal Specifications 2U Core Frequency Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes Launch to FMB 130 5 See Figure 5-19 and Table 5-19 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Management Specifications Figure 5-20. DTS: 4-Core 130W Thermal Profile 2U Notes: 1. Some of the processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. This Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 5-19 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation.
Thermal Management Specifications Table 5-19. 4-Core 130W Thermal Profile Table 2U (Sheet 2 of 2) 5.1.3.10 Power (W) Maximum TCASE (°C) Maximum DTS (°C) 85 64.9 80.0 90 65.8 81.7 95 66.7 83.5 100 67.6 85.3 105 68.5 87.1 110 69.4 88.9 115 70.3 90.6 120 71.2 92.4 125 72.1 94.2 130 73.0 96.0 4-Core 130W 1S WS Thermal Specifications Table 5-20.
Thermal Management Specifications Figure 5-21. Tcase: 4-Core 130W 1S WS Thermal Profile Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-21 for discrete points that constitute this thermal profile. 2. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-22. DTS: 4-Core 130W 1S WS Thermal Profile Notes: 1.
Thermal Management Specifications 2. 3. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-21 for discrete points that constitute thermal profile. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Table 5-21. 4-Core 130W 1S WS Thermal Profile Table 5.1.3.11 Power (W) Maximum TCASE (°C) Maximum DTS (°C) 0 42.4 42.4 5 43.3 44.
Thermal Management Specifications 2. 3. 4. 5. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. These specifications are based on final silicon characterization. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under multiple VIDs for each frequency.
Thermal Management Specifications 1. 2. 3. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. Please refer to Table 5-23 for discrete points that constitute the thermal profile. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Table 5-23.
Thermal Management Specifications Figure 5-25. Tcase: 4/2-Core 80W Thermal Profile 1U Notes: 1. Please refer to Table 5-25 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. Figure 5-26. DTS: 4-Core 80W Thermal Profile 1U Notes: 1.
Thermal Management Specifications Figure 5-27. DTS: 2-Core 80W Thermal Profile 1U Notes: 1. Some processor units may be tested to lower TDP and the TEMPERATURE_TARGET MSR will be aligned to that lower TDP. 2. Please refer to Table 5-25 for discrete points that constitute the thermal profile. 3. Implementation of this Thermal Profile should result in virtually no TCC activation.
Thermal Management Specifications Table 5-25. 4/2-Core 80W Thermal Profile Table 1U (Sheet 2 of 2) Maximum TCASE (°C) Power (W) 5.1.4 Maximum DTS (°C) 4-core 4-core 2-core 75 68.8 81.0 82.4 80 70.0 83.0 84.5 Embedded Server Processor Thermal Profiles Embedded server SKU’s target operation at higher case temperatures and/or NEBS thermal profiles for embedded communications server form factors. The thermal profiles in this section pertain only to those specific SKU’s.
Thermal Management Specifications Figure 5-28. Tcase: 8-Core LV95W Thermal Profile, Embedded Server SKU Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-28 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation.
Thermal Management Specifications Figure 5-29. DTS: 8-Core LV95W Thermal Profile, Embedded Server SKU Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-28 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation.
Thermal Management Specifications Table 5-28. 8-Core LV95W Thermal Profiles, Embedded Server SKU (Sheet 2 of 2) Maximum TCASE (ºC) 5.1.4.2 Maximum DTS (ºC) Power (W) Long Term Short Term Long Term Short Term 65 66.6 81.6 74 89 70 67.7 82.7 75 90 75 68.7 83.7 77 92 80 69.8 84.8 79 94 85 70.9 85.9 80 95 90 72.0 87.0 82 97 95 73.0 88.0 84 99 8-Core LV70W Thermal Specifications Table 5-29.
Thermal Management Specifications Notes: 1. This Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 5-30 for discrete points that constitute the thermal profile. 2. Implementation of this Thermal Profile should result in virtually no TCC activation. Refer to the Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide for system and environmental implementation details. 3.
Thermal Management Specifications Table 5-30. 8-Core LV70W Thermal Profile Table, Embedded Server SKU (Sheet 2 of 2) Maximum TCASE (ºC) 5.1.5 Maximum DTS (ºC) Power (W) Long Term Short Term Long Term Short Term 25 61.0 76.0 64 79 30 62.7 77.7 66 81 35 64.5 79.5 69 84 40 66.3 81.3 71 86 45 68.1 83.1 74 89 50 69.9 84.9 76 91 55 71.7 86.7 78 93 60 73.5 88.5 81 96 65 75.3 90.3 83 98 70 77.1 92.
5.2 Processor Core Thermal Features 5.2.1 Processor Temperature A new feature in the processor is a software readable field in the TEMPERATURE_TARGET MSR register that contains the minimum temperature at which the TCC will be activated and PROCHOT_N will be asserted. The TCC activation temperature is calibrated on a part-by-part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register.
5.2.2.1 Frequency/SVID Control The processor uses Frequency/SVID control whereby TCC activation causes the processor to adjust its operating frequency (via the core ratio multiplier) and VCC input voltage (via the SVID signals). This combination of reduced frequency and voltage results in a reduction to the processor power consumption. This method includes multiple operating points, each consisting of a specific operating frequency and voltage.
5.2.2.2 Clock Modulation Clock modulation is performed by alternately turning the clocks off and on at a duty cycle specific to the processor (factory configured to 37.5% on and 62.5% off for TM1). The period of the duty cycle is configured to 32 microseconds when the TCC is active. Cycle times are independent of processor frequency.
PROCHOT_N can allow voltage regulator (VR) thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT_N as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power.
5.2.6.2 Hybrid Closed Loop Thermal Throttling (CLTT_Hybrid) The processor periodically samples temperature from the DIMM TSoD devices over a programmable interval and interpolates gaps or the BMC/Intel ME samples a motherboard thermal sensor in the memory subsection and provides this data to the PCU via the PECI interface. This data is combined with an energy based estimations calculated by the PCU. When needed, system memory is then throttled using CAS bandwidth control.
Signal Descriptions 6 Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. 6.1 System Memory Interface Signals Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3 Signal Name DDR{0/1/2/3}_BA[2:0] Description Bank Address. Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. DDR{0/1/2/3}_CAS_N Column Address Strobe.
Signal Descriptions Table 6-2. Memory Channel Miscellaneous Signal Name Description DDR_RESET_C01_N DDR_RESET_C23_N System memory reset: Reset signal from processor to DRAM devices on the DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while DDR_RESET_C23_N is used for memory channels 2 and 3. DDR_SCL_C01 DDR_SCL_C23 SMBus clock for the dedicated interface to the serial presence detect (SPD) and thermal sensors (TSoD) on the DIMMs.
Signal Descriptions Table 6-4. PCI Express* Port 2 Signals (Sheet 2 of 2) Signal Name Table 6-5. Description PE2D_RX_DN[15:12] PE2D_RX_DP[15:12] PCIe* Receive Data Input PE2A_TX_DN[3:0] PE2A_TX_DP[3:0] PCIe* Transmit Data Output PE2B_TX_DN[7:4] PE2B_TX_DP[7:4] PCIe* Transmit Data Output PE2C_TX_DN[11:8] PE2C_TX_DP[11:8] PCIe* Transmit Data Output PE2D_TX_DN[15:12] PE2D_TX_DP[15:12] PCIe* Transmit Data Output PCI Express* Port 3 Signals Signal Name Table 6-6.
Signal Descriptions Table 6-6. PCI Express* Miscellaneous Signals (Sheet 2 of 2) Signal Name PCI Express* Hot-Plug SMBus Data: Provides PCI Express* hotplug support via a dedicated SMBus interface. Requires an external general purpose input/output (GPIO) expansion device on the platform. PEHPSDA Note: Description Refer to the appropriate Platform Design Guide (PDG) for additional implementation details. 6.3 DMI2/PCI Express* Port 0 Signals Table 6-7.
Signal Descriptions 6.5 PECI Signal Table 6-10. PECI Signals Signal Name PECI 6.6 Description PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power and error management. Details regarding the PECI electrical specifications, protocols and functions can be found in the Platform Environment Control Interface Specification. System Reference Clock Signals Table 6-11.
Signal Descriptions 6.8 Serial VID Interface (SVID) Signals Table 6-13. SVID Signals SVIDALERT_N 6.9 Serial VID alert. SVIDCLK Serial VID clock. SVIDDATA Serial VID data out. Processor Asynchronous Sideband and Miscellaneous Signals Table 6-14. Processor Asynchronous Sideband Signals (Sheet 1 of 3) Signal Name 148 Description BIST_ENABLE BIST Enable Strap. Input which allows the platform to enable or disable built-in self test (BIST) on the processor.
Signal Descriptions Table 6-14. Processor Asynchronous Sideband Signals (Sheet 2 of 3) Signal Name Description PROCHOT_N PROCHOT_N will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal can also be driven to the processor to activate the Thermal Control Circuit. This signal is sampled after PWRGOOD assertion.
Signal Descriptions Table 6-14. Processor Asynchronous Sideband Signals (Sheet 3 of 3) Signal Name Description TXT_AGENT Intel TXT Platform Enable Strap. 0 = Default. The socket is not the Intel TXT Agent. 1 = The socket is the Intel TXT Agent. In non-Scalable DP platforms, the legacy socket (identified by SOCKET_ID[1:0] = 00b) with Intel TXT Agent should always set the TXT_AGENT to 1b. On Scalable DP platforms the Intel TXT AGENT is at the Node Controller.
Signal Descriptions Table 6-16. Power and Ground Signals (Sheet 2 of 2) Signal Name Description VTTD_SENSE VSS_VTTD_SENSE VTTD_SENSE and VSS_VTTD_SENSE provide an isolated, low impedance connection to the processor I/O power plane. These signals must be connected to the voltage regulator feedback circuit, which insures the output voltage (that is, processor voltage) remains within specification. Please see the applicable platform design guide for implementation details.
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Electrical Specifications 7 Electrical Specifications 7.1 Processor Signaling The processor includes 2011 lands, which utilize various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups.
Electrical Specifications 7.1.5 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Electrical Specifications The processor core frequency is configured during reset by using values stored within the device during manufacturing. The stored value sets the lowest core multiplier at which the particular processor can operate. If higher speeds are desired, the appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits [15:0].
Electrical Specifications Table 7-1. Power and Ground Lands Power and Ground Lands VCC VCCPLL 7.1.9.2 Number of Lands 208 3 Comments Each VCC land must be supplied with the voltage determined by the SVID Bus signals. Table 7-3 Defines the voltage level associated with each core SVID pattern.Table 7-11, Figure 7-2, and Figure 7-5 represent VCC static and transient limits. VCC has a VBOOT setting of 0.0V. Each VCCPLL land is connected to a 1.
Electrical Specifications higher than the VID supported by the VR, then VR will respond with a “not supported” acknowledgement. See the VR12/IMVP7 Pulse Width Modulation Specification for further details. 7.1.9.3.1 SVID Commands The processor provides the ability to operate while transitioning to a new VID setting and its associated processor voltage rails (VCC, VSA, and VCCD). This is represented by a DC shift.
Electrical Specifications 7.1.9.3.5 SVID Power State Functions: SetPS The processor has three power state functions and these will be set seamlessly via the SVID bus using the SetPS command. Based on the power state command, the SetPS commands sends information to VR controller to configure the VR to improve efficiency, especially at light loads.
Electrical Specifications 7.1.9.3.6 SVID Voltage Rail Addressing The processor addresses 4 different voltage rail control segments within VR12 (VCC, VCCD_01, VCCD_23, and VSA). The SVID data packet contains a 4-bit addressing code: Table 7-2. SVID Address Usage PWM Address (HEX) Processor 00 Vcc 01 Vsa 02 VCCD_01 03 +1 not used 04 VCCD_23 05 +1 not used Notes: 1. Check with VR vendors for determining the physical address assignment method for their controllers. 2.
Electrical Specifications Table 7-3. VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 2 of 2) HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD HEX VCC, VSA, VCCD 0.78500 8F 0.96000 B2 1.13500 D5 1.31000 F8 1.48500 0.79000 90 0.96500 B3 1.14000 D6 1.31500 F9 1.49000 6E 0.79500 91 0.97000 B4 1.14500 D7 1.32000 FA 1.49500 6F 0.80000 92 0.97500 B5 1.15000 D8 1.32500 FB 1.50000 HEX VCC, VSA, VCCD 0.61000 6C 0.61500 6D 4B 0.
Electrical Specifications Table 7-4. Signal Description Buffer Types (Sheet 2 of 2) Signal Description DDR3 DDR3 buffers: 1.5 V and 1.35 V tolerant DMI2 Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express* 2.0 and 1.0 Signaling Environment AC Specifications. Intel QPI Current-mode 6.4 GT/s and 8.0 GT/s forwarded-clock Intel QuickPath Interconnect signaling Open Drain CMOS Open Drain CMOS (ODCMOS) buffers: 1.
Electrical Specifications Table 7-5.
Electrical Specifications Table 7-5. Signal Groups (Sheet 3 of 3) Differential/Single Ended Signals1 Buffer Type JTAG & TAP Signals Single ended CMOS1.05V Input TCK, TDI, TMS, TRST_N CMOS1.05V Input/Output PREQ_N CMOS1.05V Output PRDY_N Open Drain CMOS Input/ Output BPM_N[7:0] EAR_N Open Drain CMOS Output TDO Serial VID Interface (SVID) Signals Single ended CMOS1.
Electrical Specifications Table 7-6.
Electrical Specifications 7.4 Fault Resilient Booting (FRB) The processor supports both socket and core level Fault Resilient Booting (FRB), which provides the ability to boot the system as long as there is one processor functional in the system. One limitation to socket level FRB is that the system cannot boot if the legacy socket that connects to an active PCH becomes unavailable since this is the path to the system BIOS. See Table 7-8 for a list of output tri-state FRB signals.
Electrical Specifications Technology transitions signal. Please refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 for details on the FLEX_RATIO MSR and setting the processor core frequency. Not all operating systems can support dual processors with mixed frequencies.
Electrical Specifications Notes: 1. For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must be satisfied. 2. Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 7.9.5. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 7.7.
Electrical Specifications 7.8 DC Specifications DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (TCASE specified in Section 5), clock frequency, and input voltages. Care should be taken to read all notes associated with each specification.
Electrical Specifications 7.8.1 Voltage and Current Specifications Table 7-11. Voltage Specification Symbol Parameter VCC VID VCC VID Range VCC Core Voltage (Launch - FMB) VVID_STEP (Vcc, Vsa, Vccd) VID step size during a transition VCCPLL PLL Voltage VCCD (VCCD_01, VCCD_23) Voltage Plane Max Unit Notes1 1.35 V 2, 3 See Table 7-13, Table 7-14 and Figure 7-3, Figure 7-4 V 3, 4, 7, 8, 12, 14, 18 5.0 mV 10 Min Typ 0.6 VCC VCCPLL 0.955*VCCPLL_TYP 1.8 1.
Electrical Specifications 16. VCCD tolerance at processor pins. Tolerance for VR at remote sense is ±3.3%*VCCD. 17. The VCCPLL, VCCD01, VCCD23 voltage specification requirements are measured across vias on the platform. Choose VCCPLL, VCCD01, or VCCD23 vias close to the socket and measure with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using 1.5 pF maximum probe capacitance, and 1MΩ minimum impedance.
Electrical Specifications capable of drawing ICC_MAX for up to 5 seconds. Refer to Figure 7-5 for further details on the average processor current draw over various time durations. Table 7-13. 8/6 Core: Processor VCC Static and Transient Tolerance ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) Notes 0 VID + 0.015 VID - 0.000 VID - 0.015 1,2,3,4,5,6 5 VID + 0.011 VID - 0.004 VID - 0.019 1,2,3,4,5,6 10 VID + 0.007 VID - 0.008 VID - 0.023 1,2,3,4,5,6 15 VID + 0.003 VID - 0.012 VID - 0.
Electrical Specifications 2. 3. 4. 5. 6. Figure 7-3. This table is intended to aid in reading discrete points on graph in Figure 7-3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_VCC_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_VCC_SENSE lands. Refer to the VR12/IMVP7 Pulse Width Modulation Specification for loadline guidelines and VR implementation details.
Electrical Specifications Table 7-14. 4/2-Core: Processor VCC Static and Transient Tolerance (Sheet 2 of 2) ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) Notes 60 VID - 0.033 VID - 0.048 VID - 0.063 1,2,3,4,5,6 65 VID - 0.037 VID - 0.052 VID - 0.067 1,2,3,4,5,6 70 VID - 0.041 VID - 0.056 VID - 0.071 1,2,3,4,5,6 75 VID - 0.045 VID - 0.060 VID - 0.075 1,2,3,4,5,6 80 VID - 0.049 VID - 0.064 VID - 0.079 1,2,3,4,5,6 85 VID - 0.053 VID - 0.068 VID - 0.083 1,2,3,4,5,6 90 VID - 0.
Electrical Specifications Figure 7-4. 4/2-Core: Processor VCC Static and Transient Tolerance Loadlines Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 -VID VID +- 0.020 VID VID+- 0.000 0.000 VCC Maximum VID - 0.020 VID - 0.040 Vcc [V] VID - 0.060 VID - 0.080 VID - 0.100 VCC Typical VID - 0.120 VCC Minimum VID - 0.140 VID - 0.
7.8.2 Die Voltage Validation Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 7-15 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope. Figure 7-5. Load Current Versus Time Notes: 1. The peak current for any 5 second sample does not exceed Icc_max. 2.
Table 7-15. VCC Overshoot Specifications (Sheet 2 of 2) Symbol TOS_MAX Figure 7-6. Parameter Min Max Units Figure 25 μs 7-6 Time duration of VCC overshoot above VccMAX value at the new lighter load Notes VCC Overshoot Example Waveform VOS_MAX Voltage [V] VID + VOS_MAX VccMAX (I1) TOS_MAX 0 5 10 15 20 25 30 Time [us] Notes: 1. VOS_MAX is the measured overshoot voltage. 2. TOS_MAX is the measured time duration above VccMAX(I1). 3.
Table 7-16. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2) Symbol Parameter Min Typ Max Units Notes1 VOL Output Low Voltage (VCCD/ 2)* (RON /(RON+RVTT_TERM)) V 2, 7 VOH Output High Voltage VCCD- ((VCCD / 2)* (RON/ (RON+RVTT_TERM)) V 2, 5, 7 Reference Clock Signal RON DDR3 Clock Buffer On Resistance 21 31 Ω 6 Command Signals RON DDR3 Command Buffer On Resistance 16 24 Ω 6 RON DDR3 Reset Buffer On Resistance 25 75 Ω 6 VOL_CMOS1.
13. DRAM_PWR_OK_C{01/23}: Data Scrambling must be enabled for production environments. Disabling Data scrambling may be used for debug and testing purposes only. Operating systems with Data Scrambling off will make the configuration out of specification. Table 7-17. PECI DC Specifications Symbol Definition and Conditions Min Max Units -0.150 VTT V Figure Notes1 VIn Input Voltage Range VHysteresis Hysteresis VN Negative-edge threshold voltage 0.275 * VTT 0.
Table 7-19. SMBus DC Specifications (Sheet 2 of 2) Symbol Parameter Min Max Units V VIH Input High Voltage VOL Output Low Voltage 0.7*VTT 0.2*VTT VOH Output High Voltage VTT(max) V RON Buffer On Resistance 14 Ω IL Leakage Current Signals DDR_SCL_C{01/23}, DDR_SDA_C{01/ 23} +100 μA IL Leakage Current Signals PEHPSCL, PEHPSDA +900 μA Notes V -100 Table 7-20.
Table 7-21. Serial VID Interface (SVID) DC Specifications (Sheet 2 of 2) Symbol Parameter Min Typ Max Units Notes RON Buffer On Resistance Signals SVIDCLK, SVIDDATA 14 Ω 2 IIL Input Leakage Current Signals SVIDCLK, SVIDDATA ±900 μA 3,4 IIL Input Leakage Current Signal SVIDALERT_N ±500 μA 3,4 Notes: 1. VTT refers to instantaneous VTT. 2. Measured at 0.31*VTT 3. Vin between 0V and VTT 4. Refer to the appropriate Platform Design Guide (PDG) for routing design guidelines. Table 7-22.
1. 2. 3. 4. 5. 6. These specifications This table applies to the processor sideband and miscellaneous signals specified in Table 7-5. Unless otherwise noted, all specifications in this table apply to all processor frequencies. For Vin between 0 and Voh.For Vin between 0 and Voh. PWRGOOD Non Monotonicity duration (TNM) time is maximum 1.3 ns. These are measured between VIL and VIH.
Figure 7-7. BCLK{0/1} Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 550 + 0.5 (VHavg - 700) 450 400 250 + 0.5 (VHavg - 700) 350 300 250 mV 250 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 7-8. BCLK{0/1} Differential Clock Measurement Point for Ringback T STABLE VRB-Differential VIH = +150 mV VRB = +100 mV 0.0V VRB = -100 mV VIL = -150 mV REFCLK + Figure 7-9.
Figure 7-10. BCLK{0/1} Single Ended Clock Measurement Points for Delta Cross Point BCLK_DN VCROSS DELTA = 140 mV BCLK_DP 7.9 Signal Quality Data transfer requires the clean reception of data signals and clock signals. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swings will adversely affect system timings. Ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
7.9.3 Intel QuickPath Interconnect Signal Quality Specifications Signal Quality specifications for Differential Intel® QuickPath Interconnect Signals are included as part of the Intel QuickPath Interconnect signal quality specifications. Various scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate Platform Design Guide (PDG). 7.9.
7.9.5.2 Overshoot/Undershoot Pulse Duration Overshoot/undershoot pulse duration describes the total amount of time that an overshoot/undershoot event exceeds the overshoot/undershoot reference voltage. The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.
the overshoot specification, when you add the total impact of all overshoot events, the system may fail. A guideline to ensure a system passes the overshoot and undershoot specifications is shown below. 1. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables, OR 2. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 0.
Processor Land Listing 8 Processor Land Listing This chapter provides sorted land list in Section 8.1 and Section 8.2. Table 8-1 is a listing of all processor lands ordered alphabetically by land name. Table 8-2 is a listing of all processor lands ordered by land number. 8.1 Listing by Land Name Table 8-1. Land Name (Sheet 1 of 49) Land Name Land No. Table 8-1. Land Name (Sheet 2 of 49) Land Name Buffer Type Direction Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 3 of 49) Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 4 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 5 of 49) Land Name Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 6 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 7 of 49) Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 8 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 9 of 49) Land Name Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 10 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 11 of 49) Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 12 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 13 of 49) Land Name Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 14 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 15 of 49) Land Name Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 16 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 17 of 49) Land Name Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 18 of 49) Land Name Land No. Buffer Type Direction DDR3_ECC[7] H26 SSTL I/O DMI_TX_DP[3] C45 PCIEX O DDR3_MA_PAR B18 SSTL O TXT_PLTEN V52 CMOS I DDR3_MA[00] A19 SSTL O DRAM_PWR_OK_C01 CW17 CMOS1.5v I DDR3_MA[01] E21 SSTL O DRAM_PWR_OK_C23 L15 CMOS1.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 19 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 20 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 21 of 49) Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 22 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 23 of 49) Land Name Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 24 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name (Sheet 25 of 49) Land Name Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 26 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 27 of 49) Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 28 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 29 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 30 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 31 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 32 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 33 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 34 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 35 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 36 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 37 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 38 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 39 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 40 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 41 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 42 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 43 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 44 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 45 of 49) Land No. Table 8-1. Buffer Type Direction Land Name Land Name (Sheet 46 of 49) Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 47 of 49) Land No. Table 8-1. Buffer Type Direction Land Name (Sheet 48 of 49) Land Name Land No.
Processor Land Listing Table 8-1. Land Name Land Name (Sheet 49 of 49) Land No.
Processor Land Listing 8.2 Listing by Land Number Table 8-2. Land Number (Sheet 1 of 48) Land No. Land Name A11 DDR3_DQ[33] Table 8-2. Buffer Type Direction SSTL Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 3 of 48) Land No. Land Name AC21 VCCD_23 AC23 VCCD_23 Buffer Type Direction Table 8-2. Land Number (Sheet 4 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 5 of 48) Land No. Land Name AF22 VTTD AF24 VTTD Table 8-2. Buffer Type Direction Land Number (Sheet 6 of 48) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 7 of 48) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 9 of 48) Land No. Land Name AP6 VCC AP8 VCC Table 8-2. Buffer Type Direction Land Number (Sheet 10 of 48) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 11 of 48) Land Name Buffer Type Direction Table 8-2. Land Number (Sheet 12 of 48) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 13 of 48) Land Name BC47 RSVD BC49 SOCKET_ID[1] Buffer Type Direction CMOS I Table 8-2. Land Number (Sheet 14 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 15 of 48) Land No. Land Name BH44 BH46 Buffer Type Direction Table 8-2. Land Number (Sheet 16 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 17 of 48) Buffer Type Direction Table 8-2. Land No. Land Name BN43 VSS GND BR57 VSS GND BN45 VSS GND BR7 VCC PWR BN47 RSVD BN49 QPI0_DRX_DN[18] QPI I Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 19 of 48) Land Name Buffer Type Direction Table 8-2. Land Number (Sheet 20 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 21 of 48) Buffer Type Direction Table 8-2. Land No. Land Name CA13 VCCPLL PWR CB38 DDR0_DQ[48] SSTL I/O CA15 VCCPLL PWR CB4 DDR0_DQ[09] SSTL I/O CA17 DDR01_RCOMP[0] Analog CB40 DDR0_DQS_DN[06] SSTL I/O CA19 VSS GND CB42 DDR0_DQ[55] SSTL I/O CA21 VTTD PWR CB44 SVIDCLK ODCMOS O CA23 VTTD PWR CB46 VSS GND CA25 VCC PWR CB48 VSS GND CA27 VSS GND CB50 VSS GND I Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 23 of 48) Land Name Buffer Type Direction Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 25 of 48) Land No. Land Name Buffer Type Direction CG21 DDR0_CLK_DP[2] SSTL CG23 DDR0_CLK_DP[1] SSTL Table 8-2. Land Number (Sheet 26 of 48) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 27 of 48) Land Name Buffer Type Direction Table 8-2. Land Number (Sheet 28 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 29 of 48) Buffer Type Direction Table 8-2. Land No. Land Number (Sheet 30 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 31 of 48) Land No. Land Name Buffer Type Direction CT26 DDR1_CS_N[7] SSTL CT28 VSS GND CT30 DDR1_DQ[32] SSTL CT32 DDR1_DQS_DN[04] SSTL CT34 DDR1_DQ[34] CT36 DDR1_DQ[52] Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 33 of 48) Buffer Type Direction Table 8-2. Land No. Land Number (Sheet 34 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 35 of 48) Land No. Land Name Buffer Type Direction DA23 DDR1_MA[03] SSTL DA25 DDR1_ODT[1] SSTL DA27 DDR1_CS_N[9] SSTL DA29 DDR1_CS_N[6] SSTL Table 8-2. Land Number (Sheet 36 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 37 of 48) Buffer Type Direction Table 8-2. Land Number (Sheet 38 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 39 of 48) Buffer Type Direction Table 8-2. Land No. Land Number (Sheet 40 of 48) Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 41 of 48) Land No. Land Name H56 H58 H6 DDR3_DQS_DN[15] SSTL H8 VSS GND 232 Buffer Type Direction Table 8-2. Land Number (Sheet 42 of 48) Land No.
Processor Land Listing Table 8-2. Land No. Land Number (Sheet 43 of 48) Land Name Buffer Type Direction L5 VSS GND L51 PE3A_TX_DN[1] PCIEX3 L53 PE1B_RX_DN[4] L55 PE2A_RX_DP[0] L57 PE1B_RX_DN[6] L7 DDR3_DQ[54] Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 45 of 48) Land No. Land Name P52 PE3B_TX_DP[4] PCIEX3 P54 VSS GND 234 Buffer Type Direction P56 VSS GND P6 DDR3_DQ[51] SSTL O I/O Table 8-2. Land No.
Processor Land Listing Table 8-2. Land Number (Sheet 47 of 48) Land No. Land Name Buffer Type Direction U7 DDR2_DQ[44] SSTL U9 DDR2_DQ[55] SSTL V10 DDR2_DQ[51] V12 DDR2_DQS_DN[15] V14 V16 Table 8-2. Land Number (Sheet 48 of 48) Land No.
Processor Land Listing § 236 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One
Package Mechanical Specifications 9 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FCLGA10) package that interfaces with the baseboard via an LGA2011-0 land FCLGA10 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications 5. Reference datums 6. All drawing dimensions are in millimeters (mm). 7. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the Intel® Xeon® Processor E51600/E5-2600/E5-4600 Product Families Thermal/Mechanical Design Guide.
Package Mechanical Specifications Figure 9-2.
Package Mechanical Specifications Figure 9-3.
Package Mechanical Specifications 9.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Do not contact the Test Pad Area with conductive material. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 9-2 and Figure 9-3 for keep-out zones.
Package Mechanical Specifications 9.6 Processor Mass Specification The typical mass of the processor is currently 45 grams. This mass [weight] includes all the components that are included in the package. 9.7 Processor Materials Table 9-3 lists some of the package components and associated materials. Table 9-3. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Halogen Free, Fiber Reinforced Resin Substrate Lands 9.
Boxed Processor Specifications 10 Boxed Processor Specifications 10.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Intel® Xeon® processor E52600 product family (LGA2011-0 land FCLGA10) processors will be offered as Intel boxed processors, however the thermal solutions will be sold separately. Boxed processors will not include a thermal solution in the box.
Boxed Processor Specifications Figure 10-1. STS200C Passive/Active Combination Heat Sink (with Removable Fan) Figure 10-2. STS200C Passive/Active Combination Heat Sink (with Fan Removed) The STS200C utilizes a fan capable of 4-pin pulse width modulated (PWM) control. Use of a 4-pin PWM controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the baseboard’s ability to directly control the RPM of the processor heat sink fan. See Section 10.
Boxed Processor Specifications sink solutions. The retention solution used for the STS200P Heat Sink Solution is called the ILM Retention System (ILM-RS).The retention solution used for the STS200PNRW Narrow Heat Sink Solution is called the Narrow ILM Retention System (Narrow ILM-RS). Figure 10-3. STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks 10.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor solution. 10.2.
A B C D 8 7 6 8 7 BALL 1 CORNER POSITIONAL MARKING (FOR REFERENCE ONLY) 93.0 MAX THERMAL SOLUTION ENVELOPE AND MECHANICAL PART CLEARANCE 2X FINGER ACCESS 8 6 (51.0 ) SOCKET BODY OUTLINE (FOR REFERENCE ONLY) 2X 46.0 SOCKET ILM HOLE PATTERN 93.0 MAX THERMAL SOLUTION ENVELOPE AND MECHANICAL PART CLEARANCE (FINGER ACCESS NOT INCLUDED) The drawing contains corporation information. may not beAND reproduced, THIS DRAWING CONTAINS INTEL intel CORPORATION CONFIDENTIAL INFORMATION.
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One A B C D 8 7 6 5 8 (93.0 ) A 2X 7.05 SEE DETAIL 2X 8.80 7 12.80 (93.0 ) 6 AS VIEWED FROM PRIMARY SIDE OF MAINBOARD 2X 3.45 2X 41.46 2X 53.808 2X 92.0 2X 31.55 5 SEE DETAIL 2X 25.25 18.20 2X 3.30 2X 4.50 The drawing contains intel corporation information. contents may not reproduced, THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION.
A B C D 8 7 6 8 7 2X 5.0 4X R7.0 22.37 4X 4.8 NO ROUTE ZONE THRU ALL LAYERS 6 5 R1.00 TYP 5 AS VIEWED FROM SECONDARY SIDE OF MAINBOARD 2X 23.40 14.0 71.5 The drawing contains corporation information. Its contents not be AND reproduced, THIS DRAWING CONTAINS INTELintel CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSEDmay IN CONFIDENCE ITS CONTENTS displayed, or modified without the prior writtenWITHOUT consent of Intel Corporation.
8 7 6 76.50 R 2200 MISSION COLLEGE BLVD. P.O. BOX 58119 SANTA CLARA, CA 95052-8119 DWG. NO 2 D SHT. 4 REV SIZE DRAWING NUMBER G11950 G11950 B 1 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One A B 8 7 TOP SURFACE OF MOTHERBOARD 81.50 4.38 PRIMARY SIDE 3D HEIGHT RESTRICTION ZONES AND VOLUMETRIC SWEEPS OF LOADPLATE AND LEVER OPENING/CLOSING 6 97.0° MIN 93.00 97.0° MIN .03 4 93.
A B C D 8 7 6 8 [ B 0 -0.25 +0.000 3.602 -0.009 91.50 C ] 7 0 -0.25 TOP VIEW [3.602+0.000 -0.009 ] 91.50 +1.00 0 [0.472+0.039 -0.000 ] 4X 12.00 6 A +1.00 0 64.00 [2.520] MAX. AIRFLOW DIRECTION [0.472+0.039 -0.000 ] 4X 12.00 The drawing contains intel corporation information. Its contents may not be reproduced, THIS DRAWING CONTAINS INTEL CORPORAT ION CONFIDENTIAL INFORMATION.
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One A B C D 8 7 6 5 8 80.00 [3.150] 9 38.00 #0.50 [1.496 #0.019 ] A 7 A-A 9 80.00 [3.150] 38.00 #0.50 [1.496 #0.019 ] SECTION 6 BOTTOM VIEW FLATNESS ZONE, SEE NOTE 7 0.077 [0.0030] B SEE DETAIL 5 AIRFLOW DIRECTION A C SEE DETAIL AIRFLOW DIRECTION TOP VIEW The drawing contains intel corporation information.
Boxed Processor Specifications The drawing contains intel corporation information. Its contents may not be reproduced, displayed, or modified without the prior written consent of Intel Corporation. Figure 10-10.
Boxed Processor Specifications The drawing contains intel corporation information. Its contents may not be reproduced, displayed, or modified without the prior written consent of Intel Corporation. Figure 10-11.
Boxed Processor Specifications 10.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (ILM-RS) Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor. The standard and narrow ILM-RSs are designed to extend air-cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass. ILM-RS retention transfers load to the baseboard via the ILM Assembly.
Boxed Processor Specifications Figure 10-12. Fan Cable Connector Pin Out For 4-Pin Active Thermal Solution 10.3.1 Boxed Processor Cooling Requirements As previously stated the boxed processor will have three thermal solutions available. Each configuration will require unique design considerations. Meeting the processor’s temperature specifications is also the function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.
Boxed Processor Specifications Table 10-2. 8 Core / 6 Core Server Thermal Solution Boundary Conditions TDP Thermal Solution ΨCA2 (˚C/W) TLA 1 (˚C) Airflow 3 (CFM) Delta P (inch of H2O) Heatsink Volumetric4 (mm) 150W (WS Only) 8 Core STS200C (with fan) 0.180 40.0 Max RPM N/A 91.5x91.5x64 130W (1U) 6 and 8 Core STS200P 0.242 53.6 16 0.406 91.5x91.5x25.5 130W (1U) 6 and 8 Core STS200PNRW 0.253 52.2 14 0.347 70x106x25.5 130W (2U) 6 and 8 Core STS200C (without fan) 0.180 61.
Boxed Processor Specifications Boxed Processor • Intel® Xeon® processor E5-2600 product family • Installation and warranty manual • Intel Inside Logo Boxed Thermal Solution • Thermal solution assembly • Thermal interface material (pre-applied) • Installation and warranty manual § Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One 257
Boxed Processor Specifications 258 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One
