Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 48
Datasheet Volume One
Signal Descriptions
MEM_HOT_C01_N
MEM_HOT_C23_N
Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two
modes of operation – input and output mode.
Input mode is externally asserted and is used to detect external events such as
VR_HOT# from the memory voltage regulator and causes the processor to throttle the
appropriate memory channels.
Output mode is asserted by the processor known as level mode. In level mode, the
output indicates that a particular branch of memory subsystem is hot.
MEM_HOT_C01_N is used for memory channel 1 while MEM_HOT_C23_N is used for
memory channels 2 & 3.
MSMI_N Machine Check Exception (MCE) is signaled via this pin when eMCA2 is enabled.
PM_FAST_WAKE_N Power Management Fast Wake. Enables quick package C3 - C6 exits of all sockets.
Asserted if any socket detects a break from package C3 - C6 state requiring all sockets
to exit the low power state to service a snoop, memory access, or interrupt. Expected to
be wired-OR among all processor sockets within the platform.
PMSYNC Power Management Sync. A sideband signal to communicate power management status
from the Platform Controller Hub (PCH) to the processor.
PROCHOT_N PROCHOT_N will go active when the processor temperature monitoring sensor detects
that the processor has reached its maximum safe operating temperature. This indicates
that the processor Thermal Control Circuit has been activated, if enabled. This signal
can also be driven to the processor to activate the Thermal Control Circuit. This signal is
sampled after PWRGOOD assertion.
If PROCHOT_N is asserted at the deassertion of RESET_N, the processor will tristate its
outputs.
PWRGOOD Power Good is a processor input. The processor requires this signal to be a clean
indication that BCLK and power supplies are stable and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on until they come
within specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions from
inactive to active when all supplies except V
CCIN
are stable. V
CCIN
has a V
BOOT
of 1.7 V
volts and is included in PWRGOOD indication in this phase. However, for the active to
inactive transition, if any CPU power supply is about to fail or is out of regulation, the
PWRGOOD is to be negated.
The signal must be supplied to the processor; it is used to protect internal circuits
against voltage sequencing issues. It should be driven high throughout boundary scan
operation.
RESET_N Asserting the RESET_N signal resets the processor to a known state and invalidates its
internal caches without writing back any of their contents. Note some PLL, Intel
®
QuickPath Interconnect and error states are not affected by reset and only PWRGOOD
forces them to a known state.
RSVD RESERVED. All signals that are RSVD must be left unconnected on the board. Refer to
Section 2.2.10, “Reserved or Unused Signals” for details.
SAFE_MODE_BOOT Safe mode boot Strap. SAFE_MODE_BOOT allows the processor to wake up safely by
disabling all clock gating, this allows BIOS to load registers or patches if required. This
signal is sampled after PWRGOOD assertion. The signal is pulled down on the die, refer
to Table 2-5 for details.
SOCKET_ID[1:0] Socket ID Strap. Socket identification configuration straps for establishing the PECI
address, Intel
®
QPI Node ID, and other settings. This signal is used in combination with
FRMAGENT to determine whether the socket is a legacy socket, bootable firmware
agent is present, and DMI links are used in PCIe* mode (instead of DMI2 mode). Each
processor socket consumes one Node ID, and there are 128 Home Agent tracker
entries. This signal is pulled down on the die, refer to Table 2-5 for details.
TEST[4:0] Test[4:0] must be individually connected to an appropriate power source or ground
through a resistor for proper processor operation.
Table 3-12. Processor Asynchronous Sideband Signals (Sheet 2 of 3)
Signal Name Description