Datasheet

Intel® Xeon® Processor E5-2400 v3 Product Family 47
Datasheet Volume One
Signal Descriptions
3.9 Processor Asynchronous Sideband and
Miscellaneous Signals
SVIDCLK Serial VID clock.
SVIDDATA Serial VID data out.
Table 3-12. Processor Asynchronous Sideband Signals (Sheet 1 of 3)
Signal Name Description
BIST_ENABLE BIST Enable Strap. Input which allows the platform to enable or disable built-in self test
(BIST) on the processor. This signal is pulled up on the die, refer to Table 2-5 for details.
BMCINIT BMC Initialization Strap. Indicates whether Service Processor Boot Mode should be
used. Used in combination with FRMAGENT and SOCKET_ID inputs.
• 0: Service Processor Boot Mode Disabled. Example boot modes: Local PCH (this
processor hosts a legacy PCH with firmware behind it), Intel
®
QPI Link Boot (for
processors one hop away from the FW agent), or Intel
®
QPI Link Init (for
processors more than one hop away from the firmware agent).
• 1: Service Processor Boot Mode Enabled. In this mode of operation, the processor
performs the absolute minimum internal configuration and then waits for the
Service Processor to complete its initialization. The socket boots after receiving a
“GO” handshake signal via a firmware scratchpad register.
This signal is pulled down on the die, refer to Table 2-5 for details.
CATERR_N Indicates that the system has experienced a fatal or catastrophic error and cannot
continue to operate. The processor will assert CATERR_N for nonrecoverable machine
check errors and other internal unrecoverable errors. It is expected that every
processor in the system will wire-OR CATERR_N for all processors. Since this is an I/O
land, external agents are allowed to assert this land which will cause the processor to
take a machine check exception. This signal is sampled after PWRGOOD assertion.
On the processor, CATERR_N is used for signaling the following types of errors:
• Legacy MCERR’s, CATERR_N is asserted for 16 BCLKs.
• Legacy IERR’s, CATERR_N remains asserted until warm or cold reset.
DEBUG_EN_N Forces debug to be enabled. This allows debug to occur beginning from cold boot.
ERROR_N[2:0] Error status signals for integrated I/O (IIO) unit:
• 0 = Hardware correctable error (no operating system or firmware action necessary)
• 1 = Non-fatal error (operating system or firmware action required to contain and
recover)
• 2 = Fatal error (system reset likely required to recover)
FIVR_FAULT Indicates an internal error has occurred with the integrated voltage regulator. The
FIVR_FAULT signal can be sampled any time after 1.5 ms after the assertion of
PWRGOOD. FIVR_FAULT must be qualified by THERMTRIP_N assertion. See the Platform
Design Guide for proper connectivity.
FRMAGENT Bootable Firmware Agent Strap. This input configuration strap used in combination with
SOCKET_ID to determine whether the socket is a legacy socket, bootable firmware
agent is present, and DMI links are used in PCIe* mode (instead of DMI2 mode).
The firmware flash ROM is located behind the local PCH attached to the processor via
the DMI2 interface.This signal is pulled down on the die, refer to Table 2-5 for details.
Table 3-11. SVID Signals (Sheet 2 of 2)
Signal Name Description